參數(shù)資料
型號： XC5VLX50T-3FFG665C
廠商： Xilinx Inc
文件頁數(shù)： 53/91頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX-5 50K 665FCBGA
產(chǎn)品變化通告： Step Intro and Pkg Change 11/March/2008
標準包裝： 1
系列： Virtex®-5 LXT
LAB/CLB數(shù)： 3600
邏輯元件/單元數(shù)： 46080
RAM 位總計： 2211840
輸入/輸出數(shù)： 360
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 665-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 665-FCBGA
配用： 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
57
DCM Switching Characteristics
Table 76: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
Symbol
Description
Speed Grade
Units
-3
-2
-1
Outputs Clocks (Low Frequency Mode)
F1XLFMSMIN
CLK0, CLK90, CLK180, CLK270
32.00
MHz
F1XLFMSMAX
150.00
135.00
120.00
MHz
F2XLFMSMIN
CLK2X, CLK2X180
64.00
MHz
F2XLFMSMAX
300.00
270.00
240.00
MHz
FDVLFMSMIN
CLKDV
2.0
MHz
FDVLFMSMAX
100.00
90.00
80.00
MHz
FFXLFMSMIN
CLKFX, CLKFX180
32.00
MHz
FFXLFMSMAX
180.00
160.00
140.00
MHz
Input Clocks (Low Frequency Mode)
FDLLLFMSMIN
CLKIN (using DLL outputs)(1, 3, 4)
32.00
MHz
FDLLLFMSMAX
150.00
135.00
120.00
MHz
FCLKINLFFXMSMIN
CLKIN (using DFS outputs only)(2, 3, 4)
1.00
MHz
FCLKINLFFXMSMAX
180.00
160.00
140.00
MHz
FPSCLKLFMSMIN
PSCLK
1.00
KHz
FPSCLKLFMSMAX
550.00
500.00
450.00
MHz
Outputs Clocks (High Frequency Mode)
F1XHFMSMIN
CLK0, CLK90, CLK180, CLK270
120.00
MHz
F1XHFMSMAX
550.00
500.00
450.00
MHz
F2XHFMSMIN
CLK2X, CLK2X180
240.00
MHz
F2XHFMSMAX
550.00
500.00
450.00
MHz
FDVHFMSMIN
CLKDV
7.5
MHz
FDVHFMSMAX
366.67
333.34
300.00
MHz
FFXHFMSMIN
CLKFX, CLKFX180
140.00
MHz
FFXHFMSMAX
400.00
375.00
350.00
MHz
Input Clocks (High Frequency Mode)
FDLLHFMSMIN
CLKIN (using DLL outputs)(1, 3, 4)
120.00
MHz
FDLLHFMSMAX
550.00
500.00
450.00
MHz
FCLKINHFFXMSMIN
CLKIN (using DFS outputs only)(2, 3, 4)
25.00
MHz
FCLKINHFFXMSMAX
400.00
375.00
350.00
MHz
FPSCLKHFMSMIN
PSCLK
1.00
KHz
FPSCLKHFMSMAX
550.00
500.00
450.00
MHz
Notes:
1.
DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2.
DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3.
When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
4.
When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
to 55/45).
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