參數(shù)資料
型號: XC5VLX50T-3FFG665C
廠商: Xilinx Inc
文件頁數(shù): 52/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 50K 665FCBGA
產(chǎn)品變化通告: Step Intro and Pkg Change 11/March/2008
標準包裝: 1
系列: Virtex®-5 LXT
LAB/CLB數(shù): 3600
邏輯元件/單元數(shù): 46080
RAM 位總計: 2211840
輸入/輸出數(shù): 360
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 665-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 665-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
56
Table 75: PLL in PMCD Mode Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
TPLLCCK_REL/TPLLCKC_REL
REL Setup and Hold for all Outputs
0.00
0.60
0.00
0.60
0.00
0.60
ns
TPLLCCKO
Maximum Clock Propagation Delay
4.6
5.2
ns
CLKIN_FREQ_MAX
Maximum Input Frequency
710
645
MHz
CLKIN_FREQ_MIN
Minimum Input Frequency
1
MHz
CLKIN_DUTY_CYCLE
Allowable Input Duty Cycle: 1—49 MHz
25/75
%
Allowable Input Duty Cycle: 50—199 MHz
30/70
%
Allowable Input Duty Cycle: 200—399 MHz
35/65
%
Allowable Input Duty Cycle: 400—499 MHz
40/60
%
Allowable Input Duty Cycle: >500 MHz
45/55
%
RES_REL_PULSE_MIN
Minimum Pulse Width for RST and REL
5
ns
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