參數資料
型號： XC161CJ
廠商： INFINEON TECHNOLOGIES AG
英文描述： 16-Bit Single-Chip Microcontroller
中文描述： 16位單片機
文件頁數： 64/79頁
文件大?。?/td> 2440K
代理商： XC161CJ
XC161
Derivatives
Timing Parameters
Data Sheet
60
V2.2, 2003-06
Bypass Operation
When bypass operation is configured (PLLCTRL = 0x
B
) the master clock is derived from
the internal oscillator (input clock signal XTAL1) through the input- and output-
prescalers:
f
MC
=
f
OSC
/ ((PLLIDIV+1)
×
(PLLODIV+1)).
If both divider factors are selected as ’1’ (PLLIDIV = PLLODIV = ’0’) the frequency of
f
MC
directly follows the frequency of
f
OSC
so the high and low time of
f
MC
is defined by the
duty cycle of the input clock
f
OSC
.
The lowest master clock frequency is achieved by selecting the maximum values for both
divider factors:
f
MC
=
f
OSC
/ ((3+1)
×
(14+1)) =
f
OSC
/ 60.
Phase Locked Loop (PLL)
When PLL operation is configured (PLLCTRL = 11
B
) the on-chip phase locked loop is
enabled and provides the master clock. The PLL multiplies the input frequency by the
factor
F
(
f
MC
=
f
OSC
×
F
) which results from the input divider, the multiplication factor,
and the output divider (
F
= PLLMUL+1 / (PLLIDIV+1
×
PLLODIV+1)). The PLL circuit
synchronizes the master clock to the input clock. This synchronization is done smoothly,
i.e. the master clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of
f
MC
is constantly adjusted so it
is locked to
f
OSC
. The slight variation causes a jitter of
f
MC
which also affects the duration
of individual TCMs.
The timing listed in the AC Characteristics refers to TCPs. Because
f
CPU
is derived from
f
MC
, the timing must be calculated using the minimum TCP possible under the respective
circumstances.
The actual minimum value for TCP depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCP is lower than
for one single TCP (see formula and
Figure 15
).
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal
f
MC
. Therefore,
the number of VCO cycles can be represented as K
×
N
, where
N
is the number of
consecutive
f
MC
cycles (TCM).
相關PDF資料
PDF描述
XC161CS-32F 16-Bit Single-Chip Microcontroller with C166SV2 Core
XC164-32F 16-Bit Single-Chip Microcontroller with C166SV2 Core
XC164CM 16-bit Microcontroller
XC164CS 16-Bit Single-Chip Microcontroller
XC164CS-16F 16-Bit Single-Chip Microcontroller with C166SV2 Core
相關代理商/技術參數
參數描述
XC161CJ_02 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bi t Single-Chip Microcontroller Preliminary
XC161CJ-16F 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller with C166SV2 Core
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