- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385049 > XC161CJ (INFINEON TECHNOLOGIES AG) 16-Bit Single-Chip Microcontroller PDF資料下載
參數(shù)資料
| 型號： | XC161CJ |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller |
| 中文描述： | 16位單片機(jī) |
| 文件頁數(shù)： | 25/79頁 |
| 文件大?。?/td> | 2440K |
| 代理商： | XC161CJ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
XC161
Derivatives
Functional Description
Data Sheet
21
V2.2, 2003-06
the number of bits to be shifted. Also multiplication and most MAC instructions execute
in one single cycle. All multiple-cycle instructions have been optimized so that they can
be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles,
while the remaining 15 cycles are executed in the background. Another pipeline
optimization, the branch target prediction, allows eliminating the execution time of
branch instructions if the prediction was correct.
The CPU has a register context consisting of up to three register banks with 16 wordwide
GPRs each at its disposal. One of these register banks is physically allocated within the
on-chip DPRAM area. A Context Pointer (CP) register determines the base address of
the active register bank to be accessed by the CPU at any time. The number of register
banks is only restricted by the available internal RAM space. For easy parameter
passing, a register bank may overlap others.
A system stack of up to 32 Kwords is provided as a storage for temporary data. The
system stack can be allocated to any location within the address space (preferably in the
on-chip RAM area), and it is accessed by the CPU via the stack pointer (SP) register.
Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently
be utilized by a programmer via the highly efficient XC161 instruction set which includes
the following instruction classes:
– Standard Arithmetic Instructions
– DSP-Oriented Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes
and words. A variety of direct, indirect or immediate addressing modes are provided to
specify the required operands.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC161CS-32F | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| XC164-32F | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| XC164CM | 16-bit Microcontroller |
| XC164CS | 16-Bit Single-Chip Microcontroller |
| XC164CS-16F | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC161CJ_02 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bi t Single-Chip Microcontroller Preliminary |
| XC161CJ-16F | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller with C166SV2 Core |
| XC161CJ-16F_06 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller with C166SV2 Core |
| XC161CJ16F40FBBFXQMA1 | 制造商:Infineon Technologies AG 功能描述:16 BIT FLASH - Trays |
| XC161CJ16F40FBBFXUMA1 | 制造商:Infineon Technologies AG 功能描述:MCU 16-BIT XC166 CISC/DSP/RISC 128KB FLASH 2.5V/5V 144-PIN TQFP 制造商:Infineon Technologies AG 功能描述:16 BIT FLASH - Tape and Reel 制造商:Infineon Technologies AG 功能描述:IC MCU 16BIT 128KB FLSH 144TQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。