- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385049 > XC161CJ (INFINEON TECHNOLOGIES AG) 16-Bit Single-Chip Microcontroller PDF資料下載
參數(shù)資料
| 型號： | XC161CJ |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller |
| 中文描述： | 16位單片機 |
| 文件頁數(shù)： | 24/79頁 |
| 文件大?。?/td> | 2440K |
| 代理商： | XC161CJ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
XC161
Derivatives
Functional Description
Data Sheet
20
V2.2, 2003-06
The EBC also controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.
The TwinCAN module is connected and accessed via the LXBus.
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Figure 4
CPU Block Diagram
Based on these hardware provisions, most of the XC161’s instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of
a
d
d
CSP
IP
CPUCON1
CPUCON2
CPUID
FIFO
IFU
IDX0
IDX1
QX0
QX1
QR1
QR0
SP
SPSEG
VECSEG
TFR
STKOV
STKUN
DPP0
DPP1
DPP2
DPP3
+/-
+/-
ADU
MDL
Ones
MDH
Zeros
MAL
Division Unit
Multiply Unit
MAH
Multiply Unit
MSW
MCW
ALU
RF
+/-
+/-
PSW
MRW
MDC
Barrel-Shifter
Bit-Mask-Gen.
WB
MAC
CPU
Buffer
CP
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
IPIP
DPRAM
a
data in
data out
DMU
R15
R14
R0
R1
R15
R14
R0
R1
R15
R14
R0
R1
GGGPRs
R15
R14
R0
R1
GPRs
SRAM
d
address
d
Peripheral-Bus
PMU
Internal Program Memory
System-Bus
a
d
d
System-Bus
Prefetch Unit
Branch Unit
Return Stack
Injection/Exception
Handler
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC161CS-32F | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| XC164-32F | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
| XC164CM | 16-bit Microcontroller |
| XC164CS | 16-Bit Single-Chip Microcontroller |
| XC164CS-16F | 16-Bit Single-Chip Microcontroller with C166SV2 Core |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC161CJ_02 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bi t Single-Chip Microcontroller Preliminary |
| XC161CJ-16F | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller with C166SV2 Core |
| XC161CJ-16F_06 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:16-Bit Single-Chip Microcontroller with C166SV2 Core |
| XC161CJ16F40FBBFXQMA1 | 制造商:Infineon Technologies AG 功能描述:16 BIT FLASH - Trays |
| XC161CJ16F40FBBFXUMA1 | 制造商:Infineon Technologies AG 功能描述:MCU 16-BIT XC166 CISC/DSP/RISC 128KB FLASH 2.5V/5V 144-PIN TQFP 制造商:Infineon Technologies AG 功能描述:16 BIT FLASH - Tape and Reel 制造商:Infineon Technologies AG 功能描述:IC MCU 16BIT 128KB FLSH 144TQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。