參數(shù)資料
型號(hào)： XC161CJ
廠商： INFINEON TECHNOLOGIES AG
英文描述： 16-Bit Single-Chip Microcontroller
中文描述： 16位單片機(jī)
文件頁(yè)數(shù)： 32/79頁(yè)
文件大?。?/td> 2440K
代理商： XC161CJ
XC161
Derivatives
Functional Description
Data Sheet
28
V2.2, 2003-06
3.6
Capture/Compare Units (CAPCOM1/2)
The CAPCOM units support generation and control of timing sequences on up to
32 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered
mode). The CAPCOM units are typically used to handle high speed I/O tasks such as
pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time
bases for each capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare
registers relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose capture/
compare registers, each of which may be individually allocated to either CAPCOM timer
T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function.
All registers of each module have each one port pin associated with it which serves as
an input pin for triggering the capture function, or as an output pin to indicate the
occurrence of a compare event.
Table 6
Compare Modes
Mode 0
Compare Modes (CAPCOM1/2)
Function
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Pin toggles on each compare match;
several compare events per timer period are possible
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
only one compare event per timer period is generated
Double Register
Mode
pin toggles on each compare match;
several compare events per timer period are possible
Single Event Mode
Generates single edges or pulses;
can be used with any compare mode
Mode 1
Mode 2
Mode 3
Two registers operate on one pin;
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