參數(shù)資料
型號: WV3EG232M64STSU403D4SG
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 64M X 64 DDR DRAM MODULE, 0.65 ns, DMA200
封裝: ROHS COMPLIANT, SODIMM-200
文件頁數(shù): 13/14頁
文件大?。?/td> 194K
代理商: WV3EG232M64STSU403D4SG
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WV3EG232M64STSU-D4
August 2006
Rev. 2
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
Parameter
Symbol
403
335
Unit
Min
Max
Min
Max
Row Cycle Time
tRC
55
60
tCK
Refresh row cycle time
tRFC
70
72
ns
Row active
tRAS
40
70K
42
120K
ns
RAS# to CAS# delay
tRCD
15
18
tCK
Row precharge time
tRP
15
18
ns
Row active to row active delay
tRRD
10
12
ns
Write recovery time
tWR
15
ns
Last data into Read command
tWTR
21
ns
Clock cycle time
CL=2.5
tCK
--
6
12
ns
CL=3
5
10
-
ns
Clock high level width
tCH
0.45
0.55
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
0.45
0.55
tCK
DQS-out access time from CK/CK#
tDQSCK
-0.55
0.55
-0.6
+0.6
ns
Output data access time from CK/CK#
tAC
-0.65
0.65
-0.7
+0.7
ns
Data strobe edge to output data edge
tDQSQ
-
0.4
-
0.45
ns
Read Preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.72
1.28
0.75
1.25
tCK
DQS-in setup time
tWPRES
00
ns
DQS-in hold time
tWPRE
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
tCK
DQS falling edge to CK rising-hold time
tDSH
0.2
tCK
DQS-in high level width
tDQSH
0.35
tCK
DQS-in low level width
tDQSL
0.35
tCK
Address and control input setup time (fast)
tIS
0.6
0.75
ns
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