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參數(shù)資料
| 型號： | WV3EG232M64STSU403D4SG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.65 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 194K |
| 代理商： | WV3EG232M64STSU403D4SG |
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WV3EG232M64STSU-D4
August 2006
Rev. 2
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
IDD SPECIFICATIONS AND TEST CONDITIONS
Parameter
Symbol
Conditions
DDR333 @
CL = 2.5 Max
DDR400 @
CL = 3 Max
Unit
Operating
current:
IDD0*
One device bank active; Active-Precharge; tRC = tRC(MIN); tCK = tCK(MIN); DQ,DM
and DQS inputs change once per clock cycle; Address and control inputs
change once every two clock cycles
840
500
mA
Operating
current
IDD1*
One device bank; Active-Read-Precharge; BL=4; tRC = tRC(MIN) ; tCK = tCK(MIN);
IOUT = 0mA; Address and control inputs change once per clock cycle
1,120
660
mA
Percharge
power-down
standby current
IDD2P**
All device banks are idle; Power-down mode; tCK = tCK(MIN); CKE=LOW
40
mA
Idle standby
current
IDD2F**
CS# = HIGH; All device banks are idle; tCK = tCK(MIN); CKE=HIGH; Address
and other control inputs changing once per clock cycle. VIN = VREF for DQ,
DQS and DM
240
mA
Active power-
down standby
current
IDD3P**
One device bank active; Power-down mode; tCK = tCK(MIN); CKE=LOW
240
360
mA
Active standby
current
IDD3N**
CS# = HIGH; CKE=HIGH; One device bank active; tRC = tRAS(MAX); tCK =
tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle; Address and
other control inputs changing once per clock cycle
360
480
mA
Operating
current
IDD4R*
Burst = 2; Reads; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA
1,360
780
mA
Operating
current
IDD4W*
Burst = 2; Writes; Continuous burst; One device bank active; Address and
other control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and
DQS inputs change twice per clock cycle
1,480
880
mA
Auto refresh
current
IDD5**
tRC =tRFC(MIN)
1,640
1,760
mA
Self refresh
current
IDD6**
CKE < 0.2V
40
mA
Orerating
current
IDD7*
Four device bank interleaving Reads Burst=4 with auto precharge ERC =
tRC(MIN); tCK = tCK(MIN); Address and control inputs change only during Active
READ, or WRITE commands
3,040
1,620
mA
NOTE:
IDD specication is based on
SAMSUNG components. Other DRAM Manufacturers specication may be different.
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG232M64STSU-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| WV3EG264M64EFSU262D4-MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| WV3EG264M64EFSU262D4-SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| WV3EG264M64EFSU265D4-MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| WV3EG264M64EFSU265D4-SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
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