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參數(shù)資料
| 型號： | WV3EG232M64STSU403D4SG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.65 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 194K |
| 代理商： | WV3EG232M64STSU403D4SG |
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WV3EG232M64STSU-D4
August 2006
Rev. 2
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
IDD SPECIFICATIONS AND TEST CONDITIONS
Parameter
Symbol
Conditions
DDR333 @
CL = 2.5 Max
Unit
Operating current
- One bank Active-
Precharge
IDD0*
Operating Current: One device bank active; Active-Precharge; tRC = tRC(min);
tCK = tCK(min) DQ, DM, and DQS inputs change once per clock cycle; Address
and control inputs changing once every two clock cycle
768
mA
Operating current
- One bank operation
IDD1*
Operating Current: One device bank; Active-Read-Precharge; BL = 4; tRC =
tRC(min); tCK = tCK(min); IOUT = 0mA; Address and control inputs change once per
clock cycle
792
mA
Percharge power-
down standby current
IDD2P**
Precharge Power Down Standby Current: All device banks are idle; Power
Down mode; tCK = tCK(min); CKE = LOW
40
mA
Precharge Floating
standby current
IDD2F**
Idle Standby Current: CS#=HIGH; All device banks are idle; tCK = tCK(min) CKE
= HIGH; Address and other control inputs changing once per clock cycle.
VIN = VREF for DQ, DQS, and DM
200
mA
Active power - down
standby current
IDD3P**
Active Power Down Standby Current: One device bank active; Power Down
mode; tCK = tCK(min); CKE = LOW
88
mA
Active standby
current
IDD3N**
Active Standby Current: CS# = HIGH; CKE = HIGH; One device bank active
tRC = tRAS(max); tCK = tCK(min); DQ, DM, and DQS inputs changing twice per
clock cycle; Address and other control inputs changing once per clock cycle
360
mA
Operating current
- burst read
IDD4R*
Operating Current: Burst = 2; Reads; Continuous burst; One device bank
active; Address and other control inputs changing once per clock cycle; tCK =
tCK(min); IOUT = 0mA
832
mA
Operating current
- burst write
IDD4W*
Operating Current: Burst = 2; Writes; Continuous burst; One device bank
active; Address and other control inputs changing once per clock cycle; tCK =
tCK(min); DQ, DM, and DQS inputs change twice per clock cycle
936
mA
Auto refresh current
IDD5**
Auto-Refresh Current: tRC = tRFC(min)
1,544
mA
Self refresh current;
CKE =< 0.2V
IDD6**
Self-Refresh Current: CKE < 0.2V
40
mA
Operating current
- Four bank operation
IDD7*
Operating Current: Four device bank interleaving Reads Burst = 4 with auto
precharge; tRC = tRC(min); tCK = tCK(min); Address and control inputs only during
Active READ or WRITE commands.
2,456
mA
NOTE:
IDD specication is based on
NANYA components. Other DRAM Manufacturers specication may be different.
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3EG232M64STSU-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| WV3EG264M64EFSU262D4-MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| WV3EG264M64EFSU262D4-SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| WV3EG264M64EFSU265D4-MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| WV3EG264M64EFSU265D4-SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB- 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL |
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