參數(shù)資料
型號： W19B322MTB9G
廠商： WINBOND ELECTRONICS CORP
元件分類： PROM
英文描述： 2M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： TFBGA-48
文件頁數(shù)： 34/52頁
文件大?。?/td> 1955K
代理商： W19B322MTB9G
W19B32XMT/B
1. GENERAL DESCRIPTION
The W19B32XMT/B is a 32Mbit, 2.75~3.6 volt dual bank CMOS flash memory organized as 4M
× 8 or
2M
× 16 bits. The word-wide (× 16) data appears on DQ15-DQ0, and byte-wide (× 8) data appears on
DQ7
DQ0. The device can be programmed and erased in-system with a standard 2.75~3.6V power
supply. A 12-volt VPP is not required. The unique cell architecture of the W19B32XMT/B results in fast
program/erase operations with extremely low current consumption (compared to other comparable 3-
volt flash memory products). The device can also be programmed and erased by using standard
EPROM programmers.
2. FEATURES
Performance
2.75~3.6-volt write (program and erase)
operations
TTL compatible I/O
Manufactured on WinStack 0.18
m process
technology
Fast write operation
Available packages: 48-pin TSOP and 48-ball
TFBGA (8x11mm)
Sector erase time: 0.7 Sec (typ.)
Chip erase time: 49 Sec (typ.)
Byte programming time: 5 S (typ.)
Software Features
Read access time: 90 nS
Compatible with common Flash Memory
Interface (CFI) specification
Typical program/erase cycles: 100K
Flash device parameters stored directly on
the device
Twenty-year data retention
Ultra low power consumption
Allows software driver to identify and use a
variety of different current and future Flash
products
Active current (Read): 10 mA (typ.)
Active current (Read while Erase/Program):
21 mA (typ.)
Erase Suspend/Erase Resume
Suspends erase operations to allow
programming in same bank
Standby current: 0.2 A (typ.)
Architecture
End of program detection
Dual Bank architectures
Software method: Toggle bit/Data polling
W19B322M: bank1: 4M; bank2: 28M
Unlock Bypass Program command
W19B323M: bank1: 8M; bank2: 24M
Reduces overall programming time when
issuing multiple program command
sequences
W19B324M: bank1: 16M; bank2: 16M
Security Sector Size: 256 Bytes
The Security Sector is an OTP; once the
sector is programmed, it cannot be erased
Hardware Features
Ready/#Busy output (RY/#BY)
Simultaneous Read/write operation
Detect program or erase cycle completion
Data can be continuously read from one
bank while processing erase/program
functions in other bank with zero latency
Hardware reset pin (#RESET)
Reset the internal state machine to the
read mode
JEDEC standard byte-wide and word-wide
pinouts
#WP/ACC input pin
- 4 -
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