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參數(shù)資料
| 型號(hào)： | VNC2-64Q1B-TRAY |
| 廠商： | FTDI, Future Technology Devices International Ltd |
| 文件頁數(shù)： | 15/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC USB HOST/DEVICE CTRL 64-QFN |
| 應(yīng)用說明： | Vinculum-II IO Cell Description AppNote Vinculum-II Debug Interface Description AppNote Vinculum-II IO Mux Explained AppNote Vinculum-II PWM Example AppNote Migrating Vinculum Designs AppNote |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | Vinculum-II |
| 控制器類型： | USB 2.0 控制器 |
| 接口： | USB，主機(jī)/設(shè)備配置，UART，SPI，PWM，閃存 256K，DMA 4CH |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 電流 - 電源： | 25mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（8x8） |
| 包裝： | 托盤 |
| 其它名稱： | VNC2-64Q1A-TRAY VNC2-64Q1A-TRAY-ND |
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Copyright 2009-2011 Future Technology Devices International Limited
Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.5
Document No.: FT_000138 Clearance No.: FTDI# 143
4.2.4 Input / Output Multiplexer Module
VNC2 peripheral interfaces are UART, SPI slave0, SPI slave1, SPI master, FIFO-Asynchronous, FIFO-
Synchronous, GPIO, debug interface and PWM.
The I/O multiplexer allows the designer to select which peripherals are connected to the device I/O pins.
The selectable peripheral interfaces are only limited by the number of I/O pins available. All peripherals
are available across the package range except synchronous FIFO mode which cannot be selected on 32
pin packages. The available configurable I/O pins per package are as follows:
32 pin package – 12 I/O pins
48 pin package – 28 I/O pins
64 pin package – 44 I/O pins
Table 4.1 lists the peripherals which can be multiplexed to I/O and the maximum number of pins
required for each one. The designer can choose any mix of peripheral configurations as long as they are
within the specific package I/O pin count. Depending on the design not all 9 UART pins need to be
configured. Similarly the GIPO peripheral does not need all pins configured.
e.g. The 48 pin package has 28 I/O pins which could be configured as UART – 9 pins, SPI Master – 5
pins, FIFO Asynchronous – 12 pins and GPIO – 2 pins. This makes a total of 28 pins.
Please refer to Section 5 for a detailed description of the I/O multiplexer.
Peripherals
Maximum pins required
UART
9
SPI Slave 0
4
SPI Slave 1
4
SPI Master
5
FIFO Asynchronous
12
FIFO Synchronous
14
GPIO
40
Debug
1
PWM
8
Table 4.1 - Peripheral Pin Requirements
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