參數(shù)資料
型號(hào)： UPD98401AGD-MML
廠商： NEC Corp.
元件分類(lèi)： 圓形連接器
英文描述： Circular Connector; No. of Contacts:100; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-2 RoHS Compliant: No
中文描述： 自動(dòng)柜員機(jī)特區(qū)芯片
文件頁(yè)數(shù)： 9/36頁(yè)
文件大?。?/td> 216K
代理商： UPD98401AGD-MML
Data Sheet S12100EJ3V0DS00
9
μ
PD98401A
1.2 Bus Interface Pins
The bus interface is a general-purpose bus interface compatible with most generally used I/O buses (such as PCI,
S bus, GIO, and AP bus).
(1/3)
Pin Name
Pin No.
I/O
I/O Level
Function
AD31-AD27
AD26-AD22
AD21-AD17
AD16-AD13
AD12
AD11-AD7
AD6-AD0
3 - 7
9 - 13
16 - 20
22 - 25
28
35 - 39
42 - 48
I/O
3-state
TTL in
CMOS out
Address/Data.
AD31 through AD0 constitute a 32-bit address/data bus. These pins
are I/O pins multiplexing an address bus and a data bus. At the first
clock of input/output, AD31 through AD0 transfer an address. They
transfer data at the second clock and onward. The AD bus goes into
a high-impedance state when the
μ
PD98401A does not access the
bus.
PAR3
PAR2
PAR1
PAR0
49
50
54
55
I/O
3-state
TTL in
CMOS out
Bus Parity.
PAR pins indicate the parity of AD31 through AD0. A parity check
mode is set by GMR. Enabling or disabling parity, odd or even parity,
and word or byte parity can be specified. If byte parity is specified,
PAR3 indicates the parity of AD31 through AD24, and PAR0 indicates
the parity of AD7 through AD0. If word parity is specified, PAR3
serves as an input/output pin. It serves as an output pin when an
address is output and when data is written, and as an input pin when
data is read.
When the
μ
PD98401A does not access the bus, PAR3 through PAR0
go into a high-impedance state. Pull up these pins when they are not
used.
OE_B
56
I
TTL
Output Enable.
When this pin is low, the
μ
PD98401A uses AD31 through AD0 and
PAR3 through PAR0 as 3-state I/O pins. These pins go into a high-
impedance state while a high level is being input to OE_B. This pin is
an option pin. Fix this pin to low level in a system where it is not
necessary to forcibly set the bus of the
μ
PD98401A in a high-
impedance state by controlling this pin.
SIZE2
SIZE1
SIZE0
57
60
61
O
CMOS
Burst Size.
SIZE2 through SIZE0 indicate the size of the current DMA transfer.
These pins are used to interface a bus (such as S bus) requiring clear
burst size.
SIZE2
SIZE1
SIZE0
Function
0
0
0
1-word transfer
0
0
1
2-word burst
0
1
0
4-word burst
0
1
1
8-word burst
1
0
0
16-word burst
1
0
1
12-word burst
1
1
0
Undefined
1
1
1
Reception side byte alignment
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