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參數(shù)資料
| 型號： | UPD98401AGD-MML |
| 廠商： | NEC Corp. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:100; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-2 RoHS Compliant: No |
| 中文描述： | 自動柜員機特區(qū)芯片 |
| 文件頁數(shù)： | 7/36頁 |
| 文件大?。?/td> | 216K |
| 代理商： | UPD98401AGD-MML |
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Data Sheet S12100EJ3V0DS00
7
μ
PD98401A
1.
PIN FUNCTION
The
μ
PD98401A is housed in a package having 208 pins, of which 152 pins are function pins and 56 pins are V
DD
and GND pins.
1.1 PHY Device Interface Pin
PHY device interfaces include a UTOPIA interface through which the
μ
PD98401A transfers ATM cells with a PHY
device, and a PHY control interface by which the
μ
PD98401A controls the PHY device.
(1)
UTOPIA interface
(1/2)
Pin Name
Pin No.
I/O
I/O Level
Function
Rx7-Rx4
Rx3-Rx0
74 - 77
80 - 83
I
TTL
Receive Data Bus.
Rx7 through Rx0 constitute an 8-bit input bus which inputs data
received from a network in byte format from a PHY device. The
μ
PD98401A loads data in at the rising edge of RCLK.
RSOC
86
I
TTL
Receive Start Cell.
The RSOC signal is input in synchronization with the first byte of the
cell data from a PHY device. This signal remains high while the first
byte of the header is input to Rx7 through Rx0.
RENBL_B
85
O
CMOS
Receive Enable.
The RENBL_B signal indicates to a PHY device that the
μ
PD98401A
is ready to receive data in the next clock cycle. This signal goes high
during and after reset.
EMPTY_B/
RxCLAV
87
I
TTL
PHY Output Buffer Empty/Rx Cell Available.
This signal notifies the
μ
PD98401A that there is no cell data to be
transferred in the receive FIFO and that no receive data can be
supplied to the PHY device. When the UTOPIA interface is in the
octet-level handshake mode, this signal serves as EMPTY_B,
indicating that the data on Rx7 through Rx0 are invalid in the current
clock cycle. In the cell-level handshake mode, it serves as RxCLAV,
indicating that there is no cell to be supplied next after the transfer of
the current cell is completed.
RCLK
84
O
CMOS
Receive Clock.
This is a synchronization clock used to transfer cell data with the PHY
cell device at the recieve side. The system clock input to the CLK pin
is output from this pin as is, immediately after reset.
Tx7-Tx0
95 - 102
O
CMOS
Transmit Data Bus.
Tx7 through Tx0 constitute an 8-bit output bus which outputs transmit
data in byte format to a PHY device. The
μ
PD98401A outputs data at
the rising edge of TCLK.
TSOC
89
O
CMOS
Transmit Start of Cell.
The TSOC signal is output in synchronization with the first byte of
transmit cell data.
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