- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383984 > UPD98401AGD-MML (NEC Corp.) Circular Connector; No. of Contacts:100; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-2 RoHS Compliant: No PDF資料下載
參數(shù)資料
| 型號： | UPD98401AGD-MML |
| 廠商： | NEC Corp. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:100; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-2 RoHS Compliant: No |
| 中文描述： | 自動柜員機(jī)特區(qū)芯片 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 216K |
| 代理商： | UPD98401AGD-MML |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
Data Sheet S12100EJ3V0DS00
13
μ
PD98401A
1.4 Control Memory Interface Pins
These pins constitute an interface through which the
μ
PD98401A accesses an external control memory and a
PHY device. A 18-bit address bus and a 32-bit data bus are used. The control memory of the host is accessed only
via this interface.
Pin Name
Pin No.
I/O
I/O Level
Function
CD31-CD28
CD27-CD21
CD20-CD16
CD15-CD7
CD6-CD0
110-113
116-122
125-129
132-140
143-149
I/O
3-state
TTL in,
CMOS out
Control Memory Data.
CD31 through CD0 are 3-state I/O pins and constitute a 32-bit data
bus which is used to transfer data with the control memory or a PHY
device.
CPAR3-
CPAR0
151-154
I/O
TTL in,
CMOS out
Control Memory Parity.
CPAR3 through CPAR0 indicate the parity of CD31 through CD0 in 8-
bit units. In the read cycle, the
μ
PD98401A checks the parity (when
enabled). In the write cycle, CPAR3 through CPAR0 output the parity.
Pull up these pins when they are not used.
CA17-C11
CA10-CA4
CA3-CA0
158-164
167-173
176-179
O
CMOS
Control Memory Address.
CA17 through CA0 constitute an 18-bit address bus. They output an
address to the control memory or a PHY device during read/write
operation.
CWE_B
186
O
CMOS
Control Memory Write Enable.
CWE_B signal indicates the direction in which the control memory is
accessed.
1: Read access
2: Write access
COE_B
187
O
CMOS
Control Memory Output Enable
COE_B enables or disables data output of the control memory.
CBE_B3
CBE_B2
CBE_B1
CBE_B0
180
181
184
185
O
CMOS
Local Port Byte Enable.
read or written.
INITD
188
I
TTL
Initialization Disable.
The INITD signal is used to disable automatic initialization of the
control memory during chip test. During normal operation other than
test, directly connect INITD to GND.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD98401A | ATM SAR CHIP |
| UPD9903 | UPD9903 ANALOG SUBSCRIBER LINE LSI DIGITAL CODEC |
| UPD9903GT | UPD9903 ANALOG SUBSCRIBER LINE LSI DIGITAL CODEC |
| UPG110P | 2 to 8 GHz WIDE BAND AMPLIFIER CHIP |
| UPG133G-E1 | L-BAND SPDT SWITCH |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD98401GD-MML | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Segmentation and Reassembly Circuit |
| UPD98402 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| UPD98402A | 制造商:NEC 制造商全稱:NEC 功能描述:LOCAL ATM SONET FRAMER |
| UPD98402AGM | 制造商:NEC 制造商全稱:NEC 功能描述:LOCAL ATM SONET FRAMER |
| UPD98402AGM-KED | 制造商:NEC 制造商全稱:NEC 功能描述:LOCAL ATM SONET FRAMER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。