參數(shù)資料
型號: UPD78F0547GC(T)-UBT-A
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 14 MM, LEAD FREE, PLASTIC, LQFP-80
文件頁數(shù): 65/96頁
文件大?。?/td> 4109K
代理商: UPD78F0547GC(T)-UBT-A
Preliminary Product Information U14673EJ1V0PM00
68
PD789322,789324,789326,789327
8. RESET FUNCTION
8.1 Reset Function
The
PD789322, 789324, 789326, and 789327 can be reset using the following three signals.
(1) External reset signal input via RESET pin
(2) Internal reset by watchdog timer runaway time detection
(3) Internal reset using power-on-clear circuit (POC)
The external and internal reset signals are functionally equivalent. When RESET is input, program execution
begins from the addresses written at addresses 0000H and 0001H.
If a low-level signal is applied to the RESET pin, or if the watchdog timer overflows, a reset occurs, causing each
item of the hardware to enter the states listed in Table 8-1. While a reset is being applied, or while the oscillation
frequency is stabilizing immediately after the end of a reset sequence, each pin remains in the high-impedance state.
If a high-level signal is applied to the RESET pin, the reset sequence is terminated, and program execution begins
once the oscillation stabilization time has elapsed. A reset sequence caused by a watchdog timer overflow is
terminated automatically and again program execution begins upon the elapse of the oscillation stabilization time.
Reset by power-ON clear is cleared if the supply voltage rises beyond a specific level, and the program execution is
started after the oscillation stabilization time has elapsed.
Cautions 1. To use an external reset sequence, input a low-level signal to the RESET pin for at least 10
s.
2. When a reset is used to release STOP mode, the data of when STOP mode was entered is
retained during the reset sequence, except for the port pins, which are in the high-impedance
state.
3. The oscillation stabilization time after RESET input or the release of STOP mode by POC can
be selected from 2
15/fX or 217/fX by mask option (refer to 9. MASK OPTION).
Figure 8-1. Reset Function Block Diagram
RESET
Count clock
Reset control circuit
Watchdog timer
Stop
Over-
flow
Reset signal
Interrupt function
VDD
Power-on-clear circuit
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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