參數(shù)資料
型號: UPD78F0547GC(T)-UBT-A
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 14 MM, LEAD FREE, PLASTIC, LQFP-80
文件頁數(shù): 61/96頁
文件大?。?/td> 4109K
代理商: UPD78F0547GC(T)-UBT-A
Preliminary Product Information U14673EJ1V0PM00
64
PD789322,789324,789326,789327
(5) Key return mode register 00 (KRM00)
This register is used to set the pin that is to detect the key return signal (rising edge of port 4).
KRM00 is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 6-6. Format of Key Return Mode Register 00
Symbol
7
6
5
4
3
2
1
0
Address
After reset
R/W
KRM00
0
KRM000
FFF5H
00H
R/W
KRM000
Key return signal detection control
0
Key return signal not detected
1
Key return signal detected (port 4 falling edge detection)
Cautions 1. Always set bits 1 to 7 to 0.
2. Before setting KRM00, set (1) bit 6 (KRMK00) of MK0 to disable interrupts. To enable
interrupts, clear (0) KRMK00 after clearing (0) bit 6 (KRIF00) of IF0.
3. On-chip pull-up resistors are automatically connected in input mode to the pins specified
for key return signal detection (P40 to P43). Although these resistors are disconnected
when the mode changes to output, key return signal detection continues unchanged.
Figure 6-7. Block Diagram of Falling Edge Detection Circuit
Falling edge
detection circuit
KRMK00
KRIF00 setting signal
Standby release signal
Key return mode register 00
(KRM00)
Note
Selector
P40/KR00
P41/KR01
P42/KR02
P43/KR03
Note For selecting the pin to be used as falling edge input.
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