參數(shù)資料
型號(hào): UPD78F0547GC(T)-UBT-A
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 14 MM, LEAD FREE, PLASTIC, LQFP-80
文件頁數(shù): 33/96頁
文件大?。?/td> 4109K
代理商: UPD78F0547GC(T)-UBT-A
CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U17397EJ2V1UD
39
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins.
See Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-2. Pin I/O Circuit Types (1/2)
Pin Name
I/O Circuit Type
I/O
Recommended Connection of Unused Pins
P00/TI000
P01/TI010/TO00
5-AH
P02/SO11
5-AG
P03/SI11
P04/SCK11
P05/TI001/SSI11
P06/TI011/TO01
P10/SCK10/TxD0
P11/SI10/RxD0
5-AH
P12/SO10
P13/TxD6
5-AG
P14/RxD6
5-AH
P15/TOH0
5-AG
P16/TOH1/INTP5
P17/TI50/TO50
5-AH
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P20/ANI0 to P27/ANI7
Note
11-G
Input
<Analog setting>
Connect to AVREF or AVSS.
<Digital setting>
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P30/INTP1 to P32/INTP3
P33/TI51/TO51/INTP4
5-AH
P40 to P47
P50 to P57
5-AG
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P60/SCL0
P61/SDA0
P62/EXSCL0
13-AD
P63
13-P
Input:
Connect to EVSS.
Output: Leave this pin open at low-level output after clearing
the output latch of the port to 0.
P64 to P67
5-AG
P70/KR0 to P77/KR7
P120/INTP0/EXLVI
5-AH
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
Note P20/ANI0 to P27/ANI7 are set in the analog input mode after release of reset.
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