參數(shù)資料
型號(hào): UPD78F0547GC(T)-UBT-A
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 14 MM, LEAD FREE, PLASTIC, LQFP-80
文件頁數(shù): 19/96頁
文件大小: 4109K
代理商: UPD78F0547GC(T)-UBT-A
CHAPTER 1 OUTLINE
Preliminary User’s Manual U17397EJ2V1UD
26
1.7 Outline of Functions
(1/2)
Item
PD78F0544
PD78F0545
PD78F0546
PD78F0547
PD78F0547D
Flash memory
(self-programming
supported)
Note 1
48 KB
60 KB
96 KB
128 KB
Memory bank
Note 2
4 banks
6 banks
High-speed RAM
Note 1
1 KB
Expansion RAM
Note 1
1 KB
2 KB
4 KB
6 KB
Internal
memory
Buffer RAM
32 bytes
Memory space
64 KB
High-speed system
clock
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 4.0 to 5.5 V, 1 to 10 MHz: VDD = 2.7 to 5.5 V,
1 to 5 MHz: VDD = 1.8 to 5.5 V
Main system
clock
(oscillation
frequency)
Internal high-speed
oscillation clock
Internal oscillation
8 MHz (TYP.): VDD = 1.8 to 5.5 V
Subsystem clock
(oscillation frequency)
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.8 to 5.5 V
Internal low-speed oscillation clock
(for TMH1, WDT)
Internal oscillation
240 kHz (TYP.): VDD = 1.8 to 5.5 V
General-purpose registers
8 bits
× 32 registers (8 bits × 8 registers × 4 banks)
0.1
s (high-speed system clock: @ fXH = 20 MHz operation)
0.25
s (internal high-speed oscillation clock: @ fRH = 8 MHz (TYP.) operation)
Minimum instruction execution time
122
s (subsystem clock: @ fSUB = 32.768 kHz operation)
Instruction set
8-bit operation, 16-bit operation
Multiply/divide (8 bits
× 8 bits, 16 bits ÷ 8 bits)
Bit manipulate (set, reset, test, and Boolean operation)
BCD adjust, etc.
I/O ports
Total:
71
CMOS I/O:
66
CMOS output:
1
N-ch open-drain I/O (6 V tolerance):
4
Timers
16-bit timer/event counter: 2 channels
8-bit timer/event counter:
2 channels
8-bit timer:
2 channels
Watch timer:
1 channel
Watchdog timer:
1 channel
Timer outputs
6 (PWM output: 4, PPG output: 2)
Clock output
156.25 kHz, 312.5 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(peripheral hardware clock: @ fPRS = 20 MHz operation)
32.768 kHz (subsystem clock: @ fSUB = 32.768 kHz operation)
Buzzer output
2.44 kHz, 4.88 kHz, 9.77 kHz, 19.54 kHz
(peripheral hardware clock: @ fPRS = 20 MHz operation)
A/D converter
10-bit resolution
× 8 channels (AVREF = 2.3 to 5.5 V))
Notes 1. The internal flash memory capacity, internal high-speed RAM capacity, and internal expansion RAM
capacity can be changed using the internal memory size switching register (IMS) and the internal
expansion RAM size switching register (IXS).
2. Memory banks to be used can be changed using the memory bank select register (BANK).
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