
User’s Manual U11919EJ4V0UD
17
LIST OF FIGURES (3/3)
Figure No.
Title
Page
10-6
Format of Key Return Mode Register 00 .................................................................................................152
10-7
Block Diagram of Falling Edge Detector ..................................................................................................152
10-8
Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement ...............................154
10-9
Non-Maskable Interrupt Request Acknowledgement Timing ...................................................................154
10-10
Acknowledgement of Non-Maskable Interrupt Request...........................................................................154
10-11
Interrupt Request Acknowledgement Processing Algorithm ....................................................................156
10-12
Interrupt Request Acknowledgement Timing (Example of MOV A, r) ......................................................157
10-13
Interrupt Request Acknowledgement Timing (When Interrupt Request Flag Is Set at Last Clock During
Instruction Execution) ..............................................................................................................................157
10-14
Example of Nesting ..................................................................................................................................158
11-1
Format of Oscillation Stabilization Time Select Register .........................................................................161
11-2
Releasing HALT Mode by Interrupt..........................................................................................................163
11-3
Releasing HALT Mode by RESET Input ..................................................................................................164
11-4
Releasing STOP Mode by Interrupt .........................................................................................................166
11-5
Releasing STOP Mode by RESET Input..................................................................................................167
12-1
Block Diagram of Reset Function ............................................................................................................168
12-2
Reset Timing by RESET Input .................................................................................................................169
12-3
Reset Timing by Overflow in Watchdog Timer.........................................................................................169
12-4
Reset Timing by RESET Input in STOP Mode.........................................................................................169
13-1
Environment for Writing Program to Flash Memory .................................................................................172
13-2
Communication Mode Selection Format ..................................................................................................173
13-3
Example of Connection with Dedicated Flash Programmer.....................................................................174
13-4
VPP Pin Connection Example ...................................................................................................................176
13-5
Signal Conflict (Input Pin of Serial Interface) ...........................................................................................177
13-6
Abnormal Operation of Other Device .......................................................................................................177
13-7
Signal Conflict (RESET Pin).....................................................................................................................178
13-8
Wiring Example for Flash Writing Adapter with 3-Wire Serial I/O ............................................................179
13-9
Wiring Example for Flash Writing Adapter with UART .............................................................................180
13-10
Wiring Example for Flash Writing Adapter with Pseudo 3-Wire (When P0 Is Used)................................181
A-1
Development Tools ..................................................................................................................................208
A-2
TGB-044SAP Package Drawing (Reference) ..........................................................................................213
B-1
Distance Between In-Circuit Emulator and Conversion Adapter..............................................................214
B-2
Connection Condition of Target System (NP-H44GB-TQ) .......................................................................215