
Data Sheet E0031N30
8
μ
PD45128441, 45128841, 45128163
CONTENTS
1.
2.
3.
4.
Input / Output Pin Function ........................................................................................................... 10
Commands ...................................................................................................................................... 11
Simplified State Diagram ............................................................................................................... 14
Truth Table ...................................................................................................................................... 15
4.1 Command Truth Table............................................................................................................................ 15
4.2 DQM Truth Table ..................................................................................................................................... 15
4.3 CKE Truth Table...................................................................................................................................... 15
4.4 Operative Command Table .................................................................................................................... 16
4.5 Command Truth Table for CKE ............................................................................................................. 19
5.
6.
7.
Initialization .................................................................................................................................... 20
Programming the Mode Register ................................................................................................. 21
Mode Register ................................................................................................................................ 22
7.1 Burst Length and Sequence .................................................................................................................. 23
8.
9.
10. Auto Precharge ............................................................................................................................... 26
10.1
Read with Auto Precharge .................................................................................................................. 26
10.2
Write with Auto Precharge .................................................................................................................. 27
11. Read / Write Command Interval .................................................................................................... 28
11.1
Read to Read Command Interval ....................................................................................................... 28
11.2
Write to Write Command Interval ....................................................................................................... 28
11.3
Write to Read Command Interval ....................................................................................................... 29
11.4
Read to Write Command Interval ....................................................................................................... 30
12. Burst Termination .......................................................................................................................... 31
12.1
Burst Stop Command .......................................................................................................................... 31
12.2
Precharge Termination ....................................................................................................................... 32
Address Bits of Bank-Select and Precharge ............................................................................... 24
Precharge ........................................................................................................................................ 25
12.2.1 Precharge Termination in READ Cycle ................................................................................... 32
12.2.2 Precharge Termination in WRITE Cycle ................................................................................. 33