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參數資料
| 型號： | UPD45128163G5-A80L-9JF |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | PLASTIC, TSOP2-54 |
| 文件頁數： | 28/92頁 |
| 文件大?。?/td> | 682K |
| 代理商： | UPD45128163G5-A80L-9JF |
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Data Sheet E0031N30
28
μ
PD45128441, 45128841, 45128163
11. Read / Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed. READ will be interrupted by another READ.
The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock
without any restriction.
QB1
QB2
QB3
QB4
Hi-Z
READ A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4, /CAS latency = 2
READ B
QA1
1cycle
T9
11.2 Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write command. WRITE will be interrupted by another WRITE.
The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock
without any restriction.
DB1
DB2
DB3
DB4
Hi-Z
WRITE A
DQ
Command
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4, /CAS latency = 2
WRITE B
DA1
1cycle
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