參數(shù)資料
型號: UPD45128163G5-A80L-9JF
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M-bit Synchronous DRAM 4-bank, LVTTL
中文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: PLASTIC, TSOP2-54
文件頁數(shù): 27/92頁
文件大?。?/td> 682K
代理商: UPD45128163G5-A80L-9JF
Data Sheet E0031N30
27
μ
PD45128441, 45128841, 45128163
10.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of the t
DPL (MIN.)
after the last
data word input to the device.
DB1
DB2
DB3
DB4
Auto precharge starts
WRITA B
Hi-Z
DB1
DB2
DB3
DB4
Auto precharge starts
WRITA B
Hi-Z
DQ
Command
DQ
Command
/CAS latency = 2
/CAS latency = 3
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Burst length = 4
(t
RAS
must be satisfied)
t
DPL(MIN.)
t
DPL(MIN.)
Remark
WRITA means Write with Auto Precharge
In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means after the reference.
/CAS latency
Read
Write
2
–1
+t
DPL (MIN.)
3
–2
+t
DPL (MIN.)
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