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參數(shù)資料
| 型號： | UPD45128441G5-A80L-9JF |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | RAC5-SB(-E)(-ST) Series - Powerline Regulated AC-DC Converters; Output Voltage (Vdc): 12V; Features: Very Compact AC-DC Power Supply; 5 Watt PCB Mount Package; Universal Input Voltage Range; 3000VAC Isolation; Low Output Ripple and Noise; Short Circuit Protected; UL Certified |
| 中文描述： | 32M X 4 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| 封裝： | PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 1/92頁 |
| 文件大小： | 682K |
| 代理商： | UPD45128441G5-A80L-9JF |
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The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
MOS INTEGRATED CIRCUIT
μ
PD45128441, 45128841, 45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
DATA SHEET
Document No. E0031N30 (Ver. 3.0)
Date Published August 2001 CP (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Description
The
μ
PD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access
memories, organized as 8,388,608
×
4
×
4, 4,194,304
×
8
×
4, 2,097,152
×
16
×
4 (word
×
bit
×
bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0(A13) and BA1(A12)
Byte control (
×
16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
×
4,
×
8,
×
16 organization
Single 3.3 V
±
0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD45128841G5-A75-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128441G5-A75-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128841G5-A75L-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128841G5-A80-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128841G5-A80L-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD45128841G5-A75-9JF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 16M x 8, 54 Pin, Plastic, TSOP |
| UPD4516161AG5A109NF | 制造商:NEC Electronics Corporation 功能描述: |
| UPD4516161AG5-A10-9NF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| UPD4528BC | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD4528C | 制造商:Panasonic Industrial Company 功能描述:IC SUB:TC4528BP OR TVSTC4528BP |
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