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參數(shù)資料
| 型號： | UPD45128163-A75L |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 128兆位同步DRAM 4銀行，LVTTL |
| 文件頁數(shù)： | 7/86頁 |
| 文件大小： | 821K |
| 代理商： | UPD45128163-A75L |
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Data Sheet E0344N10 (Ver. 1.0)
7
μ
PD45128163
13. Electrical Specifications ................................................................................................................. 32
13.1
AC Parameters for Read Timing ........................................................................................................ 37
13.2
AC Parameters for Write Timing ........................................................................................................ 39
13.3
Relationship between Frequency and Latency ................................................................................ 40
13.4
Mode Register Set ............................................................................................................................... 41
13.5
Power on Sequence and CBR (Auto) Refresh .................................................................................. 42
13.6
/CS Function ........................................................................................................................................ 43
13.7
Clock Suspension during Burst Read (using CKE Function) ......................................................... 44
13.8
Clock Suspension during Burst Write (using CKE Function) ......................................................... 46
13.9
Power Down Mode and Clock Mask .................................................................................................. 48
13.10 CBR (Auto) Refresh ............................................................................................................................. 49
13.11 Self Refresh (Entry and Exit) .............................................................................................................. 50
13.12 Random Column Read (Page with Same Bank) ............................................................................... 51
13.13 Random Column Write (Page with Same Bank) ............................................................................... 53
13.14 Random Row Read (Ping-Pong Banks) ............................................................................................ 55
13.15 Random Row Write (Ping-Pong Banks) ............................................................................................ 57
13.16 Read and Write .................................................................................................................................... 59
13.17 Interleaved Column Read Cycle ......................................................................................................... 61
13.18 Interleaved Column Write Cycle ........................................................................................................ 63
13.19 Auto Precharge after Read Burst ....................................................................................................... 65
13.20 Auto Precharge after Write Burst ...................................................................................................... 67
13.21 Full Page Read Cycle .......................................................................................................................... 69
13.22 Full Page Write Cycle .......................................................................................................................... 71
13.23 Byte Write Operation ........................................................................................................................... 73
13.24 Burst Read and Single Write (Option) ............................................................................................... 75
13.25 Full Page Random Column Read ....................................................................................................... 77
13.26 Full Page Random Column Write ...................................................................................................... 79
13.27 PRE (Precharge) Termination of Burst .............................................................................................. 81
14. Package Drawing ............................................................................................................................ 83
15. Recommended Soldering Conditions ........................................................................................... 84
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| UPD45128163G5-A10LT-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| UPD45128163G5-A80T-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| UPD45128163G5-A75T-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| UPD45128163G5-A10T-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range) |
| UPD45128163G5-A80-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD45128163G5 | 制造商:Renesas Electronics Corporation 功能描述:128 MBIT SDRAM |
| UPD45128163G5-A75-9JF | 制造商:Elpida Memory Inc 功能描述:8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| UPD45128841G5-A75-9JF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 16M x 8, 54 Pin, Plastic, TSOP |
| UPD4516161AG5A109NF | 制造商:NEC Electronics Corporation 功能描述: |
| UPD4516161AG5-A10-9NF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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