參數(shù)資料
型號(hào): UPD45128163-A75L
廠商: Elpida Memory, Inc.
英文描述: 128M-bit Synchronous DRAM 4-bank, LVTTL
中文描述: 128兆位同步DRAM 4銀行,LVTTL
文件頁(yè)數(shù): 31/86頁(yè)
文件大?。?/td> 821K
代理商: UPD45128163-A75L
Data Sheet E0344N10 (Ver. 1.0)
31
μ
PD45128163
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
RP
from the precharge command.
To issue a precharge command, t
RAS
must be satisfied.
When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
WRITE
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 2
DQ
Command
D1
D2
D3
ACT
DQM
t
RP
PRE
Hi-Z
D4
D5
(t
RAS
must be satisfied)
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
WRITE
CLK
T0
T2
T1
T3
T4
T5
T6
T7
Burst length = X, /CAS latency = 3
DQ
Command
D1
D2
D3
ACT
DQM
t
RP
PRE
Hi-Z
D5
T8
D4
(t
RAS
must be satisfied)
相關(guān)PDF資料
PDF描述
UPD45128163G5-A10LT-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
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UPD45128163G5-A10T-9JF 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
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