參數(shù)資料
型號: UPD45128163-A75L
廠商: Elpida Memory, Inc.
英文描述: 128M-bit Synchronous DRAM 4-bank, LVTTL
中文描述: 128兆位同步DRAM 4銀行,LVTTL
文件頁數(shù): 1/86頁
文件大小: 821K
代理商: UPD45128163-A75L
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confirm that this is the latest version.
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availability and additional information.
Elpida Memory, Inc. 2003
MOS INTEGRATED CIRCUIT
μ
PD45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
DATA SHEET
Document No. E0344N10 (Ver.1.0)
Date Published February 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Description
The
μ
PD45128163 is high-speed 134,217,728-bit synchronous dynamic random-access memory, organized as
2,097,152
×
16
×
4 (word
×
bit
×
bank).
The synchronous DRAM achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAM is compatible with Low Voltage TTL (LVTTL).
This product is packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0(A13) and BA1(A12)
Byte control by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
×
16 organization
Single 3.3 V
±
0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
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