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參數(shù)資料
| 型號： | UPD17P136BGT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PDSO28 |
| 封裝： | 0.375 INCH, PLASTIC, SOP-28 |
| 文件頁數(shù)： | 9/25頁 |
| 文件大小： | 666K |
| 代理商： | UPD17P136BGT |
17
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Figure
20.
Write
Timing
with
Synchronous
Programmable
Flags
(FWFT
Mode)
NOTES:
1.
tSKEW1
is
the
minimum
time
between
a
rising
WCLK
edge
and
a
rising
RCLK
edge
for
OR
to
go
LOW
after
two
RCLK
cycles
plus
t
REF
.If
the
time
between
the
rising
edge
of
WLCK
and
the
rising
edge
of
RCLK
is
less
than
t
SKEW1
,
then
the
OR
deassertion
may
be
delayed
one
extra
RCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
WCLK
edge
and
a
rising
RCLK
edge
for
PAE
to
go
HIGH
during
the
current
clock
cycle.
If
the
time
between
the
rising
edge
of
WCLK
and
the
rising
edge
of
RCLK
is
less
tha
nt
SKEW2
,
then
the
PAE
deassertion
may
be
delayed
one
extra
RCLK
cycle.
3.
LD
=
HIGH,
OE
=
LOW
4
.
n=
PAE
offset,
m
=
PAF
offset,
D
=
maximum
FIFO
depth
=
257
words
for
the
IDT72V205,
513
words
for
the
IDT72V215,
1,025
words
for
the
IDT72V225,
2,04
9words
for
the
IDT72V235
and
4,097
words
for
the
IDT72V245.
5
.
Select
this
mode
by
setting
(
FL
,
RXI
,
WXI
)=
(1,0,1)
during
Reset.
W
1
W
2
W
4
W
[n
+2]
W
[D-m-1]
W
[D-m-2]
W
[D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D
0
-
D
17
RCLK
tDH
tDS
tENS
tSKEW1
REN
Q
0
-Q
17
PAF
HF
PAE
IR
tDS
tSKEW2
tA
tREF
OR
tPAES
tHF
tPAFS
tWFF
W
[D-m+2]
W
1
tENH
4294
drw
20
DATA
IN
OUTPUT
REGISTER
(2)
W
3
1
2
3
1
D-1
2
+1
]
[
W
D-1
+2
]
[
W
2
D-1
+3
]
[
W
2
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