參數(shù)資料
型號(hào): UPD17P136BGT
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PDSO28
封裝: 0.375 INCH, PLASTIC, SOP-28
文件頁(yè)數(shù): 10/25頁(yè)
文件大?。?/td> 666K
代理商: UPD17P136BGT
18
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Figure
21.
Read
Timing
with
Synchronous
Programmable
Flags
(FWFT
Mode)
NOTES:
1.
tSKEW1
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
IR
will
go
LOW
after
one
WCLK
plus
t
WFF
.If
the
time
between
the
rising
edge
of
RLCK
and
the
rising
edge
of
WCLK
is
less
than
tSKEW1
,then
the
IR
assertion
may
be
delayed
an
extra
WCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
for
PAF
to
go
HIGH
during
the
current
clock
cycle.
If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
th
an
t
SKEW2
,
then
the
PAF
deassertion
time
may
be
delayed
an
extra
WCLK
cycle.
3.
LD
=
HIGH
4
.
n=
PAE
offset,
m
=
PAF
offset,
D
=
maximum
FIFO
depth
=
257
words
for
the
IDT72V205,
513
words
for
the
IDT72V215,
1,025
words
for
the
IDT72V225,
2,04
9words
for
IDT72V235
and
4,097
words
for
IDT72V245.
5
.
Select
this
mode
by
setting
(
FL
,
RXI
,
WXI
)=
(1,0,1)
during
Reset.
WCLK
12
WEN
D
0
-
D
17
RCLK
tENS
REN
Q
0
-Q
17
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
tOHZ
tSKEW1
tENH
tDS
tDH
tOE
tA
tPAFS
tWFF
tENS
OE
tSKEW2
W
D
4294
drw
21
tPAES
W
[D-n]
W
[D-n-1]
tA
tHF
tREF
W
[D-1]
W
D
tA
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
1
tENS
D-1
]
[
W
D-1
]
[
W
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