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參數(shù)資料
| 型號： | UPD17P136BGT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PDSO28 |
| 封裝： | 0.375 INCH, PLASTIC, SOP-28 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 666K |
| 代理商： | UPD17P136BGT |
22
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
AsingleIDT72V205/72V215/72V225/72V235/72V245maybeusedwhen
theapplicationrequirementsarefor256/512/1,024/2,048/4,096wordsorless.
These FIFOs are in a single Device Configuration when the First Load (
FL),
Write Expansion In (
WXI) and Read Expansion In (RXI) control inputs are
configured as (
FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 28).
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
NOTE:
1. Do not connect any output control signals directly together.
Figure 29. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36
Synchronous FIFO Memory Used in a Width Expansion Configuration
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input Ready.
Because of variations in skew between RCLK and WCLK, it is possible for flag
assertion and deassertion to vary by one cycle between FIFOs. To avoid
problemstheusermustcreatecompositeflagsbygatingtheEmptyFlags/Output
Ready of every FIFO, and separately gating all Full Flags/Input Ready. Figure
29 demonstrates a 36-word width by using two IDT72V205/72V215/72V225/
72V235/72V245s. Any word width can be attained by adding additional
IDT72V205/72V215/72V225/72V235/72V245s. These FIFOs are in a single
Device Configuration when the First Load (
FL),WriteExpansionIn(WXI)and
Read Expansion In (
RXI) control inputs are configured as (FL, RXI,
WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (Figure
29). Please see the Application Note AN-83.
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN)
READ CLOCK (RCLK)
READ ENABLE (
REN)
LOAD (
LD)
OUTPUT ENABLE (
OE)
DATA IN (D)
DATA OUT (Q)
FULL FLAG/INPUT
READY (
FF/IR)
PROGRAMMABLE (
PAE)
HALF FULL FLAG (
HF)
EMPTY FLAG/OUTPUT
READY (
EF/OR)
PROGRAMMABLE (
PAF)
RESET (
RS)
72V205
72V215
72V225
72V235
72V245
72V205
72V215
72V225
72V235
72V245
RESET (
RS)
36
18
FF/IR
EF/OR
4294 drw 29
FL
WXI RXI
FL
WXI RXI
FF/IR
EF/OR
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN)
READ CLOCK (RCLK)
READ ENABLE (
REN)
LOAD (
LD)
OUTPUT ENABLE (
OE)
DATA IN (D0 - D17)
DATA OUT (Q0 - Q17)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE (
PAE)
HALF-FULL FLAG (
HF)
EMPTY FLAG/OUTPUT READY (
EF/OR)
PROGRAMMABLE (
PAF)
RESET (
RS)
IDT
72V205
72V215
72V225
72V235
72V245
4294 drw 28
FL
RXI
WXI
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