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參數(shù)資料
| 型號： | UPD17P136BGT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PDSO28 |
| 封裝： | 0.375 INCH, PLASTIC, SOP-28 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大小： | 666K |
| 代理商： | UPD17P136BGT |
24
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18
Synchronous FIFO Memory With Programmable Flags used in Depth Expansion Configuration
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
4294 drw 31
n
RXI
HF
72V205
72V215
72V225
72V235
72V245
WXI
FL
VCC
GND
(0,1)
72V205
72V215
72V225
72V235
72V245
RXI
WXI
FL
VCC
GND
(0,1)
PAF
HF
PAE
n
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
In FWFT mode, the FIFOs can be connected in series (the data outputs of
one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to the
sum of the depths associated with each single FIFO. Figure 31 shows a depth
expansion using two IDT72V205/72V215/72V225/72V235/72V245 devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next (“ripple down”) until it finally
appears at the outputs of the last FIFO in the chain–no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethedata
word appears at the outputs of one FIFO, that device’s
OR line goes LOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for
ORof
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO’s
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLK istheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW1
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock, for the
OR flag.
The“rippledown”delayisonlynoticeableforthefirstwordwrittentoanempty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configurationwill“bubbleup”fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFO of the chain, that FIFO’s
IRlinegoesLOW,enablingtheprecedingFIFO
to write a word to fill it.
Forafullexpansionconfiguration,theamountoftimeittakesfor
IRofthefirst
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock, for the
IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
end of the chain and free locations to the beginning of the chain.
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