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參數(shù)資料
| 型號： | UPD16878GS-BGG |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動(dòng)電路 |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 242K |
| 代理商： | UPD16878GS-BGG |
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Data Sheet S15974EJ1V0DS
24
μ
PD16878
ELECTRICAL CHARACTERISTICS
DC Characteristics (Unless otherwise specified, V
DD
= 3.3 V, V
M
= 6.0 V, V
REF
= 250 mV, T
A
= 25
°
C, f
CLK
= 4 MHz,
C
OSC
= 33 pF, C
FIL
= 1000 pF, EVR = 100 mV (0000))
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Off V
M
pin current
I
MO(RESET)
No load, reset period
1.0
μ
A
V
DD
pin current
I
DD
Output open
3.0
mA
V
DD
pin current
I
DD(RESET)
Reset period
100
μ
A
High level input voltage
V
IH
0.7 V
DD
V
Low level input voltage
V
IL
0.3 V
DD
V
Input hysteresis voltage
V
H
LATCH, SCLK, SDATA, V
D
,
RESET, OSC
IN
300
mV
V
OM
α
(H)
, V
OM
β
(H)
5th byte
0.9 V
DD
V
Monitor output voltage 1
(EXT
α
,
β
)
V
OM
α
(L)
, V
OM
β
(L)
5th byte
0.1 V
DD
V
V
OEXP(H)
Pull up (V
DD
)
V
DD
V
Monitor output voltage 2
(EXP0 to EXP3 : open drain)
V
OEXP(L)
I
OEXP
= 100
μ
A
0.1 V
DD
V
High level input current
I
IH
V
IN
= V
DD
0.06
mA
Low level input current
I
IL
V
IN
= 0 V
1.0
μ
A
Reset pin high level input
current
I
IH(RST)
V
RST
= V
DD
1.0
μ
A
Reset pin low level input
current
I
IL(RST)
V
RST
= 0
1.0
μ
A
Input pull down resistor
R
IND
LATCH, SCLK, SDATA, V
D
50
200
k
H bridge ON resistance
Note 1
R
ON
I
M
= 100 mA
3.5
5.0
f
OSC(1)
DATA: 00000 (4th byte)
0
Chopping frequency (internal
oscillation: C
OSC
= 100 pF)
f
OSC(2)
DATA: 11111 (4th byte)
100
124
150
kHz
Step frequency
f
STEP
Minimum step
4
kHz
V
D
delay time
Note 2
t
VD
250
ns
Sine wave peak output
current
Note 3
I
M
L = 25 mH/R = 100
(1 kHz)
EVR = 200 mV (1010)
R
S
= 6.8
, f
OSC
= 64 kHz
52
mA
FIL pin voltage
V
EVR
EVR = 200 mV (1010)
370
400
430
mV
FIL pin step voltage
Note 4
V
EVRSTEP
Minimum step
20
mV
AC Characteristics (Unless otherwise specified, V
DD
= 3.3 V, V
M
= 6.0 V, T
A
= 25
°
C, f
CLK
= 4 MHz)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
H bridge output circuit turn on
time
t
ONH
I
M
= 100 mA
Note 5
1.0
2.0
μ
s
H bridge output circuit turn off
time
t
OFFH
I
M
= 100 mA
Note 5
1.0
2.0
μ
s
Notes 1.
Total of ON resistance at top and bottom of output H bridge
2.
By OSC
IN
and V
D
sync circuit
3.
FB pin is monitored.
4.
FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin.
5.
10 to 90% of the pulse peak value without filter capacitor (C
FIL
)
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