參數(shù)資料
型號: UPD16878GS-BGG
廠商: NEC Corp.
英文描述: MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
中文描述: 單片四H橋驅(qū)動電路
文件頁數(shù): 16/32頁
文件大?。?/td> 242K
代理商: UPD16878GS-BGG
Data Sheet S15974EJ1V0DS
16
μ
PD16878
Table 5-6. 7th Byte Data Configuration (Initial data)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Data
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
Remark
Bits D4 to D7 : Reference voltage 2 (EVR
β
2
)
Bits D0 to D3 : Reference voltage 1 (EVR
β
1
)
<8th byte>
The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H.
If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the
checksum output pin (EXT pin) is kept
L
.
(2) Standard data input
<1st byte>
The 1st byte specifies the type of data and whether the EXP pin output is used, such as when the initial data is
input.
Table 5-7. 1st Byte Data Configuration
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Data
1
1
1
0
0 or 1
0 or 1
0 or 1
0 or 1
The EXP pin goes low (current sink) when the input data is
0
, and high (high impedance state) when the input
data is
1
. Input
0
to bit D4.
<2nd byte>
The 2nd byte specifies the rotation direction of the
α
channel, enables output of the
α
channel, and the number of
pulses (126 pulses MAX.) during the 1V
D
period (in 1 cycle of FF2) of the
α
channel.
Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is
0
; it is in the reverse direction (CCW mode) when the bit is
1
.
Bit D6 is used to enable the output of the
α
channel. The
α
channel enters the high impedance state when this bit
is
0
; it is in conduction mode when the bit is
1
.
The number of pulses is set by bits D0 to D5. It is set by 6 bits in terms of software. However, the actual circuit
uses an 8-bit counter with the low-order two bits fixed to
0
. Therefore, the number of pulses that is actually
generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x
2. The number of
pulses can be set to a value in the range of 0 to 126, in units of 2 pulses.
相關(guān)PDF資料
PDF描述
UPD16878 MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
UPD16879GS-BGG MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
UPD16879 MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
UPD1703C-011 PHASE LOCKED LOOP FREQUENCY SYNTHESIZER FM/AM DIGITAL TUNING SYSTEM CONTROLLER CMOS LSI
UPD1703C-013 PHASE LOCKED LOOP FREQUENCY SYNTHESIZER FM/AM DIGITAL TUNING SYSTEM CONTROLLER CMOS LSI
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD16879 制造商:NEC 制造商全稱:NEC 功能描述:MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
UPD16879GS-BGG 制造商:NEC 制造商全稱:NEC 功能描述:MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
UPD16882 制造商:NEC 制造商全稱:NEC 功能描述:MONOLITHIC CD-ROM/DVD-ROM 3-PHASE SPINDLE MOTOR DRIVER
UPD16882GS 制造商:NEC 制造商全稱:NEC 功能描述:MONOLITHIC CD-ROM/DVD-ROM 3-PHASE SPINDLE MOTOR DRIVER
UPD16886 制造商:NEC 制造商全稱:NEC 功能描述:MONOLITHIC 1.5-CHANNEL H BRIDGE DRIVER CIRCUIT FOR CAMERAS