參數(shù)資料
型號(hào): TZA1038HW,118
廠商: NXP Semiconductors
文件頁數(shù): 7/45頁
文件大?。?/td> 0K
描述: IC DVD SIGNAL PROC 48-HTQFP
標(biāo)準(zhǔn)包裝: 2,500
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-HTQFP
包裝: 帶卷 (TR)
其它名稱: 935273843118
TZA1038HW-T
TZA1038HW-T-ND
2003 Sep 03
15
Philips Semiconductors
Product specication
High speed advanced analog DVD signal
processor and laser supply
TZA1038HW
7.2.8
INTERFACE TO THE SYSTEM CONTROLLER
Programming the registers of TZA1038HW is done via a
serial bus (see Fig.7). The circuitry is formed by a serial
input shift register and a number of registers that store the
data. The registers can always be programmed,
irrespective of STANDBY mode.
If required, the bus lines can be connected in parallel with
an I2C-bus. The protocol needs no switching of the data
line during SICL = HIGH. This means that other I2C-bus
devices will not recognise any START or STOP
commands. Control words addressed to TZA1038HW
should go uniquely with the SILD signal. When
SILD = HIGH, the TZA1038HW will not respond to any
signal on SIDA or SICL.
During a transmission, the serial data is first stored in an
input shift register. At the rising edge of SILD, the content
of the input register is copied into the addressed register.
This is also the moment the programmed information
becomes effective.
The input pins have CMOS compatible threshold levels for
both 3.3 and 5 V supplies.
handbook, full pagewidth
MGW496
tload(H)
SICL
SIDA
SILD
A3
D0 D1 D2 D3 D4 D5
D7 D8 D9 D10
D6
D11 A0
A1 A2
D0 D1 D2 D3
A2
A1
D4
A3
Fig.7 Two word transmission.
7.3
Control registers
The TZA1038HW is controlled by serial registers. To keep programming fast and efficient, the control bits are sent in
16-bit words. Four bits of the word are used for the address and for each address there are 12 data bits.
Table 1
Overview of control parameters
SYMBOL
PARAMETER
VALUES
REGISTER
BITS
Data path
G1 (A1)
gain of rst RF amplier stage
(or linear amplication)
0, 6 and 12 dB (1
×, 2× and 4×)
3
11 and 10
G2 (A2)
gain of second RF amplier
stage (or linear amplication)
6, 12, 18 and 24 dB (2
×, 4×, 8× and 16×)
3
9 and 8
G3 (A3)
gain of third RF amplier
stage (or linear amplication)
0 to 13 dB in steps of 0.8 dB (1
× to 4×)3
7 to 4
GRFSUM
(ARFSUM)
gain of RFSUM input stage (or
linear amplication)
6, 0, 6, 12 and 18 dB
(0.5
×,1×,2×,4× and 8×)
0
7 to 5
BWRF
bandwidth limitation in
RF path
f0(RF) = 12 to 145 MHz
14
6 to 0
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