參數(shù)資料
型號: TVP5154PNPG4
廠商: Texas Instruments, Inc.
英文描述: 4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER WITH INDEPENDENT SCALERS AND FAST LOCK
中文描述: 4通道低功耗PAL / NTSC制式/ SECAM制式,帶有獨立的定標器和視頻解碼器快速鎖定
文件頁數(shù): 52/78頁
文件大?。?/td> 824K
代理商: TVP5154PNPG4
www.ti.com
9.2.61 Interrupt Enable Register A
Address
C1h
Default
00h
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A–MARCH 2006–REVISED JULY 2006
7
6
5
4
3
2
1
0
Reserved
Lock interrupt
enable
Cycle complete
interrupt enable
Bus error
interrupt enable
Reserved
FIFO threshold
interrupt enable
Line interrupt
enable
Data interrupt
enable
Lock interrupt enable:
0 = Disabled (default)
1 = Enabled
Cycle complete interrupt enable:
0 = Disabled (default)
1 = Enabled
Bus error interrupt enable:
0 = Disabled (default)
1 = Enabled
FIFO threshold interrupt enable:
0 = Disabled (default)
1 = Enabled
Line interrupt enable:
0 = Disabled (default)
1 = Enabled
Data interrupt enable:
0 = Disabled (default)
1 = Enabled
The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits
loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
Conversely, bits loaded with a 0 mask the corresponding interrupt condition from generating an interrupt
on the external pin. This register only affects the interrupt on the external terminal, it does not affect the
bits in interrupt status register A. A given condition can set the appropriate bit in the status register and not
cause an interrupt on the external terminal. To determine if this device is driving the interrupt terminal
either perform a logical AND of interrupt status register A with interrupt enable register A, or check the
state of the interrupt A bit in the interrupt configuration register at address C2h.
Internal Control Registers
52
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