參數(shù)資料
型號: TVP5154PNPG4
廠商: Texas Instruments, Inc.
英文描述: 4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER WITH INDEPENDENT SCALERS AND FAST LOCK
中文描述: 4通道低功耗PAL / NTSC制式/ SECAM制式,帶有獨(dú)立的定標(biāo)器和視頻解碼器快速鎖定
文件頁數(shù): 51/78頁
文件大?。?/td> 824K
代理商: TVP5154PNPG4
www.ti.com
9.2.59 Teletext Filter Control Register
Address
BBh
Default
00h
9.2.60
Address
Default
Interrupt Status Register A
C0h
00h
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A–MARCH 2006–REVISED JULY 2006
7
6
5
4
3
2
1
0
Reserved
Filter logic
Mode
TTX filter 2 enable
TTX filter 1 enable
Filter logic: Allows different logic to be applied when combining the decision of filter 1 and filter 2 as follows:
00 = NOR (default)
01 = NAND
10 = OR
11 = AND
Mode:
0 = Teletext WST PAL mode B (2 header bytes) (default)
1 = Teletext NABTS NTSC mode C (5 header bytes)
TTX filter 2 enable:
0 = Disabled (default)
1 = Enabled
TTX filter 1 enable:
0 = Disabled (default)
1 = Enabled
If the filter matches or if the filter mask is all 0s, a true result is returned.
7
6
5
4
3
2
1
0
Lock state interrupt
Lock interrupt
Reserved
FIFO threshold interrupt
Line interrupt
Data interrupt
Lock state interrupt:
0 = TVP5154 is not locked to the video signal (default)
1 = TVP5154 is locked to the video signal.
Lock interrupt:
0 = A transition has not occurred on the lock signal (default).
1 = A transition has occurred on the lock signal.
FIFO threshold interrupt:
0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h (default).
1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h.
Line interrupt:
0 = The video line number has not yet been reached (default).
1 = The video line number programmed in address CAh has occurred.
Data interrupt:
0 = No data is available (default).
1 = VBI data is available either in the FIFO or in the VBI data registers.
The interrupt status register A can be polled by the host processor to determine the source of an interrupt.
After an interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s).
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Internal Control Registers
51
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