參數(shù)資料
型號: TVP5154PNPG4
廠商: Texas Instruments, Inc.
英文描述: 4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER WITH INDEPENDENT SCALERS AND FAST LOCK
中文描述: 4通道低功耗PAL / NTSC制式/ SECAM制式,帶有獨(dú)立的定標(biāo)器和視頻解碼器快速鎖定
文件頁數(shù): 15/78頁
文件大?。?/td> 824K
代理商: TVP5154PNPG4
www.ti.com
5
I
2
C Host Interface
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A–MARCH 2006–REVISED JULY 2006
The I
2
C standard consists of two signals, serial input/output data line (SDA) and input/output clock line
(SCL), which carry information between the devices connected to the bus. The input pins I2CA0 and
I2CA1 are used to select the slave address to which the device responds. Although the I
2
C system can be
multimastered, the TVP5154 decoder functions as a slave device only.
Both SDA and SCL must be connected to IOVDD via pullup resistors. When the bus is free, both lines are
high. The slave address select terminals (I2CA0 and I2CA1) enable the use of four TVP5154 decoders on
the same I
2
C bus. At the trailing edge of reset, the status of the I2CA0 and I2CA1 lines are sampled to
determine the device address used.
Table 5-1
summarizes the terminal functions of the I
2
C-mode host
interface.
Table 5-2
shows the device address selection options.
Table 5-1. I
2
C Terminal Description
SIGNAL
I2CA0
I2CA1
SCL
SDA
TYPE
I
I
DESCRIPTION
Slave address selection
Slave address selection
Input/output clock line
Input/output data line
I/O (open drain)
I/O (open drain)
Table 5-2. I
2
C Host Interface Device Addresses
A6
1
1
1
1
A5
0
0
0
0
A4
1
1
1
1
A3
1
1
1
1
A2
1
1
1
1
A1 (I2CA1)
0
0
1
1
A0 (I2CA0)
0
1
0
1
R/W
1/0
1/0
1/0
1/0
HEX
B9/B8
BB/BA
BD/BC
BF/BE
Data transfer rate on the bus is up to 400 kbit/s. The number of interfaces connected to the bus is
dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the
high period of the SCL, except for start and stop conditions. The high or low state of the data line can only
change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the
SCL is high indicates an I
2
C start condition. A low-to-high transition on the SDA line while the SCL is high
indicates an I
2
C stop condition.
Every byte placed on the SDA must be eight bits long. The number of bytes that can be transferred is
unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is
generated by the I
2
C master.
To simplify programming of each of the four decoder channels, a single I
2
C write transaction can be
transmitted to any one or more of the four cores in parallel. This reduces the time required to download
firmware or to configure the device when all channels are to be configured in the same manner. It also
enables the addresses for all registers to be common across all decoders.
I
2
C sub-address 0xFE contains four bits, with each bit corresponding to one of the decoder cores. If this
bit is set, I
2
C write transactions are sent to the corresponding decoder core. If the bit is 0, the
corresponding decoder does not receive the I
2
C write transactions.
I
2
C sub-address 0xFF contains four bits, with each bit corresponding to one of the decoder cores. If this
bit is set, I
2
C read transactions are sent to the corresponding decoder core. Note, only one of the bits in
this register should be set at a given time, ensuring that only one decoder core is accessed at a time for
read operations. If more than one bit is set, the lowest set bit number corresponds to the core that
responds to the read transaction.
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15
I
2
C Host Interface
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