參數(shù)資料
型號(hào): TVP5154PNPG4
廠商: Texas Instruments, Inc.
英文描述: 4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER WITH INDEPENDENT SCALERS AND FAST LOCK
中文描述: 4通道低功耗PAL / NTSC制式/ SECAM制式,帶有獨(dú)立的定標(biāo)器和視頻解碼器快速鎖定
文件頁數(shù): 13/78頁
文件大?。?/td> 824K
代理商: TVP5154PNPG4
www.ti.com
4.13 Active Video (AVID) Cropping
V
HSYNC
Active Video Area
AVID Cropped Area
AVID
Stop
AVID
Start
VBLK
Start
VBLK
Stop
4.14 Embedded Syncs
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A–MARCH 2006–REVISED JULY 2006
AVID cropping provides a means to decrease the amount of video data output. This is accomplished by
horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. The
horizontal AVID cropping is controlled using registers 11h and 12h for start pixels MSB and LSB,
respectively.
Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID
cropping is controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and
19h.
Figure 4-3
shows an AVID application.
AVID cropping can be independently controlled for scaled (registers 25h, 26h, 29h, and 2Ah) and
unscaled (registers 11h thru 14h) data streams. AVID start and stop must be changed in multiples of two
pixels to ensure correct UV alignment.
Additionally, AVID start and stop can be configured to include the SAV- and EAV-embedded sync signals
or to exclude them, and to either include or exclude ITU656 ancillary data.
Figure 4-3. AVID Application
Standards with embedded syncs insert SAV and EAV codes into the data stream at the beginning and end
of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V
change on EAV.
Table 4-4
gives the format of the SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line
and field counter varies depending on the standard. Please refer to ITU-R BT.656 for more information on
embedded syncs.
The P bits are protection bits:
P3 = V x or
H P2 = F x or
H P1 = F x or
V P0 = F x or
V x or H
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Functional Description
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