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參數(shù)資料
| 型號： | TVP5040PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 87/101頁 |
| 文件大?。?/td> | 464K |
| 代理商： | TVP5040PFP |
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2–70
2.13.59 FIFO Control
VIP address
1B6h
PHI address
B6h
I2C address
B6h
7
6
5
4
3
2
1
0
CCD reset
Read in Progress
RAM Test
TTX PHI Output Enable
FIFO Reset
FIFO reset
When a 1 is written to this register bit, the FIFO is flushed. This is done by clearing the read
and write pointers to zero, clearing the Tx count to zero, and clearing all status flags. This
bit is automatically cleared back to 0.
TTX PHI output enable
A 1 in this register enables access to the teletext data in the FIFO through the parallel host
port or I2C interface and disables access from the output formatter. A 0 disables access
from the parallel host port or I2C interface and enables access from the output formatter.
The default value is one.
RAM test
Setting this bit high allows the external processor to write data into the FIFO. In this mode,
data from the TXP is ignored. This allows the micro to test the RAM by writing and reading
test patterns. The default value is zero.
Read in progress
This bit indicates that the first byte of a teletext transaction has been read, but the last byte
has not been read. This bit can be used to verify data alignment as it is read from the FIFO.
CCD reset
When a 1 is written to this register bit, the closed caption register is reset. Also, the flag is
cleared to 0. This bit is automatically cleared back to 0.
2.13.60 FIFO RAM Test
VIP address
1B7h
PHI address
B7h
I2C address
B7h
7
6
5
4
3
2
1
0
FIFO RAM test register provides diagnostic capability into the internal teletext FIFO. This register can be written
sequentially with a block of data. The data is read back using the teletext FIFO data register at address B0h to verify
the correct operation of the FIFO.
2.13.61 Interrupt Status Register A
VIP address
1C0h
PHI address
C0h
I2C address
C0h
7
6
5
4
3
2
1
0
TvpLOCK state
TvpLOCK interrupt
Cycle complete
Bus error
CC odd field
CC even field
Teletext threshold
Teletext data
Teletext Data
*0 = Teletext data buffer empty or we have not reached the video line number that equals
the interrupt line number register
1 = Teletext data buffer contains a complete transaction and the video line number =
interrupt line number
Note this bit can be configured to occur whenever the video line number = interrupt line
number register regardless of the data.
Teletext Threshold
*0 = Threshold not reached
1 = Teletext data in buffer has reached configurable threshold
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