參數(shù)資料
型號(hào): TVP5040PFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: POWER, PLASTIC, TQFP-80
文件頁數(shù): 44/101頁
文件大?。?/td> 464K
代理商: TVP5040PFP
2–31
2.8.4.4 FIFO Status 1 Register
The FIFO status 1 register returns the status of the FIFO DMA channels in TVP5040.
7
6
5
4
3
2
1
0
Undefined
PRESENT-D (0)
R/W-C (1)
PRESENT-C (1)
R/W-B (0)
PRESENT-B (1)
R/W-A (1)
PRESENT-A (1)
R/W: This bit is set to 1 if the FIFO is a read port.
PRESENT: This bit is set to 1 if the FIFO is present, otherwise it is set to 0.
COMMAND PHASE
DATA PHASE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
0
1
D
0
1
0
1
There is no address phase associated with reading the VBI FIFO 1 register. This register is read-only and is always
set to 0x37.
2.8.4.5 VBI FIFO (FIFO A)
The VBI FIFO stores sliced VBI data in the format described in section 2.9.1. Data may be read from the FIFO at the
average rate of 1 data byte per 3 cycles (1 data cycles, 2 wait cycles) when the VIPCLK is at maximum speed.
COMMAND PHASE
DATA PHASE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VBI FIFO read
0
1
0
1
0
D
There is no address phase associated with reading the VBI FIFO. FIFO polling is implemented.
2.8.5
VIP Microcode Write Operation (FIFO B)
The data written during the microcode write operation will be written to the TVP5040 program RAM. During the write
cycle the microprocessor will reset and point to location zero in the program and will remain reset. Upon completion
of the write operation, a microprocessor CLEAR-RESET operation is required. This is performed by writing into the
7F register to clear reset and resume the microprocessor function. (There is no specific data requirement to be written
into the 7F register, any data will resume the microprocessor function.)
COMMAND PHASE
DATA PHASE (toTVP5040)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Microcode write
0
1
0
1
0
1
0
1
D
Program RAM FIFO for write
COMMAND PHASE
ADDRESS PHASE
DATA PHASE (to TVP5040)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Clear reset
0
1
0
1
0
1
D
There is no address phase associated with writing to the program RAM.
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