參數(shù)資料
型號(hào)： TVP5040PFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁數(shù)： 31/101頁
文件大小： 464K
代理商： TVP5040PFP
2–19
2.7.2
I2C Write Operation
The Data transfers occur utilizing the following illustrated formats.
An I2C master initiates a write operation to TVP5040 by generating a start condition followed by TVP5040s I2C
address 101110X , the X in the TVP5040 address is 0 when VC3 terminal is tied low and is 1 when VC3 terminal is
tied high, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the
TVP5040, the master presents the subaddress of the register, or the first of a block of registers it wants to write,
followed by one or more bytes of data, MSB first. The TVP5040 acknowledges each byte after completion of each
transfer. The I2C master terminates the write operation by generating a stop condition.
STEP 1
0
I2C Start (master)
S
STEP 2
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
0
X
0
STEP 3
9
I2C Acknowledge (slave)
A
STEP 4
7
6
5
4
3
2
1
0
I2C Write Register address (master)
addr
STEP 5
9
I2C Acknowledge (slave)
A
STEP 6
7
6
5
4
3
2
1
0
I2C Write data (master)
Data
STEP 7
9
I2C Acknowledge (slave)
A
STEP 8
0
I2C Stop (master)
P
Repeat steps 6 and 7 until all data has been written.
2.7.3
I2C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates
a write operation to the TVP5040 by generating a start condition followed by the TVP5040s I2C address 101110X,
in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledge from the TVP5040, the
master presents the subaddress of the register, or the first of a block of registers it wants to read. After the cycle is
acknowledged, the master terminates the cycle immediately by generating a stop condition. The second phase is the
data phase. In this phase, a I2C master initiates a read operation to TVP5040 by generating a start condition followed
by the TVP5040s I2C address 101110X, in MSB first bit order, followed by a 1 to indicate a read cycle. After an
acknowledge from TVP5040, the I2C master receives one or more bytes of data from the TVP5040. The I2C master
acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the
TVP5040 to the master, the master generates a not acknowledge followed by a stop.
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