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參數(shù)資料
| 型號： | TVP5040PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 37/101頁 |
| 文件大?。?/td> | 464K |
| 代理商： | TVP5040PFP |
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2–24
2.8
VIP Host Interface Port
The TVP5040 host interface is configured for VIP operation by attaching external pullup and pulldown resistors to
the GLCO, PALI, and FID terminals. The following is the combination of resistors required to select I2C host mode,
where 0=pulldown and 1=pullup.
GLCO
PALI
FID
VIP host port enabled
0
1
0
The video interface port is a standard interface, conforming to Video Interface Port VIP Specification Version 2.0
between a video enabled graphics device and one or more video devices. The video port of VIP transports various
types of real time signal streams. Signal names in parenthesis ( ) denote the signal name referenced in the VIP
specification. Five terminals are required for host port transfers: VC3, VC0, VC1, VC2, and INTREQ. Table 2–4
summarizes the terminal functions of the VIP-mode host interface.
2.8.1
VIP Host Port Terminal Description
Table 2–4. VIP Host Port Terminal Description
SIGNAL
TYPE
DESCRIPTION
VC3 (VIPCLK)
O
VIP host clock (25-33 MHz)
VC0,VC1
(HAD[0:1] )
I/O
Host address/data bus
VC0 = (HAD_0)
VC1 = (HAD_1)
VC2 (HCTL)
I/O (open drain)
Host Control. This includes the symbolic signals of VFRAME, DTACK and VSTOP.
INTREQ (VIRQ)
O (nominal open drain)
Interrupt request
VC3 (VIPCLK) is the host port clock, specified from 25-33 MHz. VIPCLK can be from any source.
VC0 and VC1 (HAD[0:1]) is a two wire bus, used to transfer commands, addresses and data between master and
slave devices.
VC2 (HCTL) is a shared control terminal. It is driven by the master to initiate and terminate data transfers. It is driven
by the slave to terminate and add wait states to data transfers. Because it is a shared control signal, special attention
must be given to its generation to avoid bus conflicts.
INTREQ is a nominally open drain terminal used to signal interrupts to the host controller. This terminal may be
configured as a conventional CMOS I/O buffer (non-open drain) if desired using the interrupt configuration register
at subaddress C2. Contention is possible if multiple devices are connected to the INTREQ signal and it is configured
in non-open drain mode.
Upon power up, the VIP module outputs remain in the high impedance state until a request from the motherboard
signals the module to begin driving the bus.
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