參數(shù)資料
型號(hào)： TVP5040PFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁數(shù)： 46/101頁
文件大小： 464K
代理商： TVP5040PFP
2–33
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tsu(1)
A[1:0],D[0:7], RD/WR setup until DS low
5
ns
td(1)
Delay DTACK low after DS low
0
ns
th(1)
A[1:0], D[0:7], RD/WR hold after DS high
5
ns
td(2)
Delay DS high after DTACK low
5
ns
td(3)
Delay DTACK high after DS high
0
ns
td(4)
Delay DS low(next cycle) after DTACK high
5
ns
tsu(2)
(Read cycle) D[7:0] setup until DTACK low
10
ns
th(2)
(Read cycle) D[7:0] hold after DS high
0
ns
td(1)
th(1)
td(2)
tsu(1)
tsu(2)
th(2)
Write Data
Read Data
A[1:0]
D[7:0]
WRITE
RD/WR (VC1)
DS (VC2)
DTACK (VC0)
D[7:0]
READ
CS (VC3)
td(4)
td(3)
Figure 2–33. Parallel Host Interface A Timing
2.8.8
Parallel Host Interface B
Parallel host interface B is compatible with the Video Electronics Standards Association (VESA
) video module
interface (VMI) proposal version 1.4 mode B. The terminal descriptions are defined in Table 2–8.
Table 2–8. Parallel Host Interface B Terminal Description
TERMINAL
SIGNAL
TYPE
DESCRIPTION
A[1:0]
HA[1:0]
I
Address bus from host
D[7:0]
HD[7:0]
I/O
Bidirectional data bus
VC3
CS
I
Chip select, active low
VC2
RD
I
Read, active low
VC1
WR
I
Write, active low
VC0
RDY
O
Ready, active high
INTREQ
O
Interrupt request, open drain by default, active low, pullup resistor required can be configured,
subaddress C2, as a conventional CMOS buffer, active high, no pullup required.
The parallel host interface B timing is shown in Figure 2–34. The cycle is initiated by the host when VC2-RD OR
VC1-WR transitions low. The TVP5040 responds by pulling VC0-RDY low. The TVP5040 will then set VC0-RDY to
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