
2–60
2.13.28 Interrupt Enable Register B
VIP address
11Dh
PHI address
1Dh
I2C address
1Dh
7
6
5
4
3
2
1
0
Software init occurred
Macrovision
detect changed
TVP command
ready
Field rate
changed
Line alternation
changed
Color lock
changed
H/V lock
changed
TV/VCR
changed
Software init
0 = Software init interrupt source masked
(default)
1 = Software init interrupt source enabled
Macrovision Detect Changed
0 = Macrovision detect interrupt source masked (default)
1 = Macrovision detect interrupt source enabled
TVP Command Ready
0 = TVP command interrupt source masked
(default)
1 = TVP command interrupt source enabled
Field Rate Changed
0 = Field rate interrupt source masked
(default)
1 = Field rate interrupt source enabled
Line Alternation Changed
0 = Line alternation interrupt source masked
(default)
1 = Line alternation interrupt source enabled
Color Lock Changed
0 = Color lock interrupt source masked
(default)
1 = Color lock interrupt source enabled
H/V Lock Changed
0 = H/V lock interrupt source masked
(default)
1 = H/V lock interrupt source enabled
TV/VCR Changed
0 = TV/VCR interrupt source masked
(default)
1 = TV/VCR interrupt source enabled
The interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for interrupt
B. Bits loaded with a 1 allows the corresponding interrupt condition to generate an interrupt on the external pin.
Conversely bits loaded with a 0 masks the corresponding interrupt condition from generating an interrupt on the
external pin. Note this register only affects the external terminal, it does not affect the bits in the interrupt status
register. A given condition can set the appropriate bit in the status register and not cause an interrupt on the external
pin. To determine if this device is driving the interrupt terminal, either perform a logical AND of the interrupt status
register B with the interrupt enable register B or check the state of the interrupt B bit in the interrupt B active register.
2.13.29 Interrupt Configuration Register B
VIP address
11Eh
PHI address
1Eh
I2C address
1Eh
7
6
5
4
3
2
1
0
Reserved
Interrupt polarity B
Interrupt Polarity
0 = Interrupt B is active low.
1 = Interrupt B is active high. (default)
Must be same as interrupt polarity A bit at bit 0 of
interrupt configuration register A at address C2
The interrupt configuration register B is used to configure the polarity of interrupt B on the external interrupt terminal.
Note that when the interrupt B is configured for active low, the terminal is driven low when active and 3-state when
inactive (open-collector). Conversely, when the interrupt B is configured for active high, it is driven high for active and
driven low for inactive.