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參數(shù)資料
| 型號： | TVP5040CPFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 51/109頁 |
| 文件大小： | 568K |
| 代理商： | TVP5040CPFP |
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2–30
General TVP5040 Registers: The bulk of the TVP5040 register space consists of status and control registers that
are available to the host in I2C, VIP, and VMI modes. Information on the register functions is available in section 2.14
VIP subaddresses 100-1FF.
COMMAND PHASE
ADDRESS PHASE
DATA PHASE (from TVP5040)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
General TVP5040 register read
0
1
0
1
A
D
COMMAND PHASE
ADDRESS PHASE
DATA PHASE (to TVP5040)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
General TVP5040 register write
0
1
0
1
A
D
2.8.4.2 No Latency Read
In order to avoid holding up the host port due to the extended wait states of a normal read operation, a special no
latency read mode is implemented in TVP5040.
NOTE:This special mode is not part of the VIP specification.
The no latency read consists of two zero wait-state phases separated by an idle period, during which the host may
perform other operations. The first phase identifies the register address to be read. In response to the first phase read,
the TVP5040 outputs data immediately from an internal intermediate buffer. Note that the data in the intermediate
data buffer is not from the register currently being addressed.
Following completion of the first phase, the host must wait for 64
s to ensure that the data requested in the first phase
is available in the intermediate data buffer. Any attempt to use the host port during this time results in slave termination
by TVP5040. The host then initiates the second phase to read the data from the intermediate buffer.
COMMAND PHASE
ADDRESS PHASE
DATA PHASE (from TVP5040)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
No latency read
Phase 1
0
1
0
1
0
A
X
COMMAND PHASE
ADDRESS PHASE
DATA PHASE (from TVP5040)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
No latency read
Phase 2
0
1
0
1
A
D
A pipelined read of several registers can be done by having the host initiate a series of back-to-back phase 1 reads,
with each phase 1 read occurring at least 64
s from the previous phase 1 read. With this, for every phase 1 read,
the TVP5040 returns the data for the previous phase 1 read. Finally, at the end, the host must initiate a phase 2 read
to get the data for the last read transaction.
COMMAND PHASE
ADDRESS PHASE
DATA PHASE (from TVP5040)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
No latency read (pipelined)
Phase 1
0
1
0
1
0
A
X
COMMAND PHASE
ADDRESS PHASE
DATA PHASE (from TVP5040)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
No latency read (pipelined)
Phase 1
0
1
0
1
A
D
COMMAND PHASE
ADDRESS PHASE
DATA PHASE (from TVP5040)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
No latency read (pipelined)
Phase 2
0
1
0
1
X
D
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參數(shù)描述 |
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