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參數(shù)資料
| 型號(hào)： | TVP5040CPFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 59/109頁 |
| 文件大?。?/td> | 568K |
| 代理商： | TVP5040CPFP |
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2–37
2.8.10 Parallel Host Interface Register Map
The parallel host interface (PHI) module contains only four registers that are directly accessible to the host (see
Figure 2–36). The address register holds an indirect address for internal register access. When the host accesses
the data register the PHI module reads or writes the internal register selected by the indirect address register. Two
other registers are provided for direct access. The FIFO register provides direct access to the VBI FIFO. The other
direct access register is the status/interrupt register. This register contains the state of the interrupt sources.
00
Address Register
A[1:0]
01
Data Register
10
FIFO
11
Status Register
Figure 2–36. PHI Address Register Map
Normally, read or write operations require two accesses. To read the FIFO register, set A[1:0] to 2’b10, and perform
a read cycle. The FIFO read data is placed on the D[7:0] bus. To read/write the status/interrupt register, set A[1:0]
to 2’b11 and perform the read/write cycle. The read/write data is appropriately muxed to/from the external data bus.
Indirect register read/write
All PHI accesses except for the VBI FIFO and the status/interrupt register require a two-step operation. To access
an indirect register, the desired internal address must first be written to the address register of the PHI. This is done
by setting A[1:0] to 00 and performing a write cycle with D[7:0] = indirect register address. To write to an indirect
register, the second step consists of writing the desired data to PHI address 01. To read an indirect register, the second
step consists of reading the requested data from address 01.
Read Indirect Register
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
Register address
Step 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read register data
0
1
Data from register
Write Indirect Register
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
Register address
Step 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register data
0
1
Data to register
Latency
PHI accesses to indirect addresses 00-8F require special consideration due to response latencies of up to 64
s for
these addresses. Latency occurs between steps 1 and 2 for a read operation, and following step 2 for a write
operation. To avoid violating PHI cycle time requirements the host can poll the cycle complete bit in the PHI status
register following step 1 for a read or step 2 for a write. Alternatively, the cycle complete enable bit in the interrupt
enable register (indirect address C1) can be set to generate an interrupt for the host when an access has been
completed.
PHI accesses to indirect addresses 90-CF occur with minimal latency and interrupts are not generated for the
completion of access cycles to these addresses.
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