參數(shù)資料
型號: TVP5040CPFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號轉換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: POWER, PLASTIC, TQFP-80
文件頁數(shù): 70/109頁
文件大?。?/td> 568K
代理商: TVP5040CPFP
2–47
2.13.3 VIP Subsystem Vendor ID
VIP address
004 - 005h
PHI address
NA
I2C address
NA
Address
7
6
5
4
3
2
1
0
004
Loaded from UV [7:0] pins on powerup reset
005
Loaded from Y [7:0] pins on powerup reset
This field identifies the subsystem manufacturer (for example, the board manufacturer). Address 005 is the MSB. The
values of this field are set at the device power up or reset by sampling the state of Y[7:0] and UV[7:0] terminals. The
Y[7:0] and UV[7:0] terminals may be tied to pullup or pulldown resisters to determine a fixed value for the subsystem
vendor ID.
The default can be overwritten by writing a different value to the register as the first access to this register after reset.
This register is read-only after the first write or read.
2.13.4 VIP Subsystem Device ID
VIP address
006 - 007h
PHI address
NA
I2C address
NA
Address
7
6
5
4
3
2
1
0
006
Loaded from D [7:0] pins on powerup reset
007
Loaded from A[1:0], VSYN, HSYN, Y[9:8], and UV[9:8] pins on powerup reset.
This field identifies the subsystem device. Address 007 is the MSB. This field is one time writeable, similar to the
subsystem vendor ID.
2.13.5 VIP Power State
VIP address
008h
PHI address
NA
I2C address
NA
7
6
5
4
3
2
1
0
0
Power state
This register is both readable and writable. When read, this register indicates the current power state of TVP5040.
Bit 0 and bit 1 define four possible power states.
0 0 =
P0 state. Fully on. This is the normal operation mode. (default)
0 1 =
P1 state. Not supported
1 0 =
P2 state. Not supported.
1 1 =
P3. A/D converters are turned off and the internal clock is reduced to minimum. Power may or may not be removed.
Writing to these two bits forces TVP5040 to one of the four power states as defined above.
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