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| 型號(hào)： | TTRN0110G |
| 廠商： | Lineage Power |
| 英文描述： | 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer(10 G位/秒時(shí)鐘合成器，16:1數(shù)據(jù)多路復(fù)用器) |
| 中文描述： | 10 Gb /秒時(shí)鐘合成器，16:1數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘合成器，16:1數(shù)據(jù)多路復(fù)用器） |
| 文件頁數(shù)： | 9/30頁 |
| 文件大小： | 633K |
| 代理商： | TTRN0110G |
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Advance Data Sheet
August 2000
TTRN0110G
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
9
Lucent Technologies Inc.
Pin Information
(continued)
Table 3. Pin Descriptions—622.08 Mbits/s and Related Signals
(continued)
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
indicates an internal pull-up resistor on this pin. I
d
indicates an internal pull-down resistor on this pin.
Table 4. Pin Descriptions—Reset
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
indicates an internal pull-up resistor on this pin. I
d
indicates an internal pull-down resistor on this pin.
Pin
R13
P13
Symbol
*
CK622P
CK622N
Type
O
Level
LVDS
Name/Description
Clock Output (622 MHz).
622 MHz differential clock output.
Note that this clock frequency will scale by 15/14 when
operating at the FEC rate.
Phase Adjust.
Adjusts phase of CK622 in 90 degree steps.
M15
L14
R11
P11
PHADJ[0]
PHADJ[1]
CK155P
CK155N
I
t
CMOS
O
LVDS
Clock Output (155 MHz).
155 MHz differential clock output.
Note that this clock frequency will scale by 15/14 when
operating at the FEC rate.
Enable CK155P/N Clock Output (Active-Low).
0 = CK155P/N buffer enabled
1 or no connection = CK155P/N buffer powered off
Parallel Input Clock (622 MHz).
622 MHz differential clock
input used to register parallel data when using forward
directional clocking mode. Note that this clock frequency will
scale by 15/14 when operating at the FEC rate.
Clock Mode Select.
Selects clocking method for data transfer
mode.
00 = forward directional clocking
01 = clockless transfer
11 or no connections = contraclocking
Loss of Lock (Active-Low).
0 = PLL out of lock
External Center.
Centers the pointers in the parallel data
storage element.
Data Storage Overflow.
Indicates (active high) when an
overflow has occurred in the parallel data storage element.
Reference Clock Input (622.08 MHz or 155.52 MHz).
Note that this clock frequency must scale by 15/14 when
operating the device at the FEC rate.
Reference Clock Frequency.
Selects frequency of
REFCLKP/N.
0 = 155 MHz
1 or no connection = 622 MHz
Loop Filter PLL.
Connect LFP and LFN to loop filter (see
Figure 3, page 11).
Resistor Reference LVDS.
LVDS bias reference resistor.
Connect a
TBD
k
resistor to V
CCD
.
K13
ENCK155N
I
u
CMOS
R12
P12
PICLKP
PICLKN
I
LVDS
H15
J15
CLKMOD[0]
CLKMOD[1]
I
u
CMOS
G12
LCKLOSSN
O
CMOS
K15
EXTCNTR
I
d
CMOS
J14
OVRFLW
O
CMOS
N14
M14
REFCLKP
REFCLKN
I
LVDS
L15
REFFREQ
I
u
CMOS
F15
E15
F12
LFP
LFN
I
Analog
RREFLVDS
I
Analog
Pin
H14
Symbol
*
RESETN
Type
I
u
Level
CMOS
Name/Description
Reset (Active-Low).
Resets all synchronous logic. During a
reset, the true data outputs are in the low state and the barred
data outputs are in the high state. Reset must be held active low
for a minimum of 6.4 ns while the internal oscillator is active.
0 = reset
1 or no connection = normal operation
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