參數(shù)資料
型號： TTRN0110G
廠商： Lineage Power
英文描述： 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer(10 G位/秒時鐘合成器，16:1數(shù)據(jù)多路復用器)
中文描述： 10 Gb /秒時鐘合成器，16:1數(shù)據(jù)復用器（10政位/秒時鐘合成器，16:1數(shù)據(jù)多路復用器）
文件頁數(shù)： 2/30頁
文件大?。?/td> 633K
代理商： TTRN0110G
TTRN0110G
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
Advance Data Sheet
August 2000
2
Lucent Technologies Inc.
Table of Contents
Contents
Page
Features ...................................................................................................................................................................1
Applications ..............................................................................................................................................................1
Description ................................................................................................................................................................1
Pin Information .........................................................................................................................................................4
Functional Overview ...............................................................................................................................................11
FEC Rate Support ..................................................................................................................................................11
Clock Synthesizer Operation ..................................................................................................................................11
Clock Synthesizer Loop Filter ..............................................................................................................................11
Clock Synthesizer Settling Time ..........................................................................................................................12
Loss of Lock Indicator (LCKLOSSN) ...................................................................................................................12
Clock Synthesizer Generated Jitter .....................................................................................................................12
Clock Synthesizer Jitter Transfer .........................................................................................................................13
Multiplexer Operation .............................................................................................................................................14
10 GHz Clock Output Enable (ENCK10G) ...........................................................................................................14
Loopback 10 GHz Data Output (LBDP/N, ENLBDN) ...........................................................................................14
Reset (RESETN) ..................................................................................................................................................14
Clocking Modes and Timing Adjustments ..............................................................................................................15
Forward Directional 622 Clocking Mode (CLKMOD[1:0] = 00, EXTCNTR, PICLKP/N, OVRFLW) .....................15
Forward Directional 311 Clocking Mode (CLKMOD[1:0] = 10, EXTCNTR, PICLKP/N, OVRFLW) .....................15
Contradirectional Clocking Mode (CLKMOD[1:0] = 01, PHADJ[1:0], EXTCNTR) ...............................................16
Clockless Transfer Mode (CLKMOD[1:0]= 11, EXTCNTR) .................................................................................17
CML Output Structure (Used on Pins D10GP/N, CK10GP/N, LBDP/N) .................................................................18
Absolute Maximum Ratings ....................................................................................................................................19
Handling Precautions .............................................................................................................................................19
Operating Conditions ..............................................................................................................................................19
Electrical Characteristics ........................................................................................................................................20
Reference Frequency (REFCLKP/N, REFFREQ) (Standard SONET Rate) ........................................................20
Reference Frequency (REFCLKP/N, REFFREQ) (FEC Rate) ............................................................................20
LVDS, CMOS, CML Input and Output Pins .........................................................................................................21
Timing Characteristics ............................................................................................................................................24
Transmit Timing ...................................................................................................................................................24
Outline Diagram ......................................................................................................................................................28
198-Pin BGA ........................................................................................................................................................28
Ordering Information ...............................................................................................................................................29
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