參數(shù)資料
型號(hào)： TTRN0110G
廠商： Lineage Power
英文描述： 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer(10 G位/秒時(shí)鐘合成器，16:1數(shù)據(jù)多路復(fù)用器)
中文描述： 10 Gb /秒時(shí)鐘合成器，16:1數(shù)據(jù)復(fù)用器（10政位/秒時(shí)鐘合成器，16:1數(shù)據(jù)多路復(fù)用器）
文件頁(yè)數(shù)： 12/30頁(yè)
文件大小： 633K
代理商： TTRN0110G
TTRN0110G
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
Advance Data Sheet
August 2000
12
Lucent Technologies Inc.
Clock Synthesizer Operation
(continued)
Clock Synthesizer Settling Time
The clock synthesizer will acquire phase/frequency lock after a valid REFCLKP/N signal is applied. The actual time
to acquire lock is a function of the loop bandwidth selected. The loop will acquire lock within 5 ms when using the
external loop bandwidth components corresponding to a corner of less than 8 MHz.
Loss of Lock Indicator (LCKLOSSN)
The LCKLOSSN pin indicates (active-low) when the clock synthesizer has exceeded phase-lock limits with the
incoming REFCLKP/N phase. The lock detect function compares the phases of the input 155 MHz or 622 MHz
clock at the REFCLKP/N pins with the internally generated 622 MHz output clock at the CK622P/N pin. When the
phase difference in the two signals is close to zero as determined by a second internal phase detector and filter,
the lock detect signal LCKLOSSN is set to a logic high. When the phase difference between the two signals is
changing at a rate exceeding the filter's cutoff frequency, the TTRN0110G is declared out of lock and LCKLOSSN
is set to a logic low. If a set of highly damped phase-locked loop parameters is chosen, LCKLOSSN may exhibit
more than one positive edge transition during the acquisition process before a steady logic-high state is achieved.
Upon a transition from the out-of-lock condition to the in-lock condition, the parallel data storage element pointers
are centered.
Clock Synthesizer Generated Jitter
The clock synthesizer’s generated jitter performance meets the requirements shown in Table 7. These specifica-
tions apply to the jitter generated at the 10 GHz clock pins CK10GP/N when the jitter on the reference clock
REFCLKP/N is within the specifications given in Table 10 on page 20, and the loop filter components are chosen to
provide a loop bandwidth of less than 8 MHz.
Table 7. Clock Synthesizer Generated Jitter Specifications
* This denotes the device specification for system SONET/SDH compliance when the loop filter in Table 6
and Figure 3 is used.
Parameter
Typical
Max
(Device)
*
0.09
Unit
Generated Jitter (p-p) SONET Rate:
Measured with 50 kHz to 80 MHz Bandpass Filter
1 UI = 1/9.95328 GHz
Generated Jitter (p-p) FEC Rate:
Measured with
kHz to
MHz Bandpass Filter
1 UI = (14/15)(9.95328 GHz)
TBD
UIp-p
TBD
0.09
UIp-p
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