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參數(shù)資料
| 型號： | TTRN0110G |
| 廠商： | Lineage Power |
| 英文描述： | 10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer(10 G位/秒時鐘合成器，16:1數(shù)據(jù)多路復(fù)用器) |
| 中文描述： | 10 Gb /秒時鐘合成器，16:1數(shù)據(jù)復(fù)用器（10政位/秒時鐘合成器，16:1數(shù)據(jù)多路復(fù)用器） |
| 文件頁數(shù)： | 11/30頁 |
| 文件大?。?/td> | 633K |
| 代理商： | TTRN0110G |
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Advance Data Sheet
August 2000
TTRN0110G
10 Gbits/s Clock Synthesizer, 16:1 Data Multiplexer
11
Lucent Technologies Inc.
Functional Overview
The TTRN0110G performs the clock synthesis and 16:1 data multiplexing operations required to support
10 Gbits/s* OC-192/STM-64 applications compliant with Telcordia Technologiesand ITU standards. Parallel 622
Mbits/s data is clocked into an input register. Both forward directional and contradirectional clocking modes are
supported as well as a clockless data transfer mode. The data is then multiplexed into a 10 Gbits/s serial stream
and output buffered for interfacing to a laser driver. A 10 GHz clock is synthesized from a reference clock and is
used to retime the serial data. The 10 GHz clock is optionally available as an output.
FEC Rate Support
The TTRN0110G will support both the normal OC-192/STM-64 rate of 9.9532 GHz and the forward error correction
(FEC) rate of 10.6642 GHz. The FECN pin selects the rate at which the part is operating. Throughout this docu-
ment, most specifications are given in terms of the normal operating rate only. All frequency-based specifications
are to be multiplied by 15/14 when operating at the FEC rate and all time-based specifications, with the exception
of electrical signal rise and fall times, are to be multiplied by 14/15 when operating at the FEC rate. For example,
the reference clock would need to be applied at 166.628 MHz or 666.515 MHz and the parallel data interface
would operate at 666.515 MHz when FECN = 0.
Clock Synthesizer Operation
The clock synthesizer uses a PLL to synthesize a 10 GHz clock from a reference frequency. A 622 MHz clock
derived from the 10 GHz synthesized clock may be used to clock in the parallel data in contradirectional clocking
applications.
Clock Synthesizer Loop Filter
A typical loop filter that provides adequate damping for less than 0.1 dB of jitter peaking is shown in Figure 3. Con-
nect the filter components to LFP and LFN. The component values can be varied to adjust the loop dynamic
response (see Table 6).
Table 6. Clock Synthesizer Loop Filter Component Values
Capacitor C1 should be either ceramic or nonpolar.
5-8061(F).c
Figure 3. Clock Synthesizer Loop Filter Components
* The OC-192/STM-64 data rate of 9.95328 Gbits/s is typically approximated as 10 Gbits/s in this document when referring to the application
rate. Similarly, the low-speed parallel interface data rate of 622.08 Mbits/s is typically approximated as 622 Mbits/s. The exact frequencies are
used only when necessary for clarity.
Components
C1
C2, C3
R1
Values for 8 MHz Loop Bandwidth
TBD
μ
F ± 10%
TBD
pF ± 20%
TBD
± 5%
C
3
C
2
C
1
R
1
LFN
LFP
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